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Vasileios KalintirisVasileios Kalintiris
Vasileios Kalintiris
authored and
Vasileios Kalintiris
committedMay 12, 2015
[mips][FastISel] Handle calls with non legal types i8 and i16.
Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 llvm-svn: 237121
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‎llvm/lib/Target/Mips/MipsFastISel.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1000,7 +1000,9 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
10001000
}
10011001
}
10021002
}
1003-
if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {
1003+
if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1004+
(ArgVT == MVT::i8)) &&
1005+
VA.isMemLoc()) {
10041006
switch (VA.getLocMemOffset()) {
10051007
case 0:
10061008
VA.convertToReg(Mips::A0);

‎llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll

Lines changed: 184 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,36 @@
55
; RUN: -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
66
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2
77

8+
declare void @xb(i8)
9+
10+
define void @cxb() {
11+
; ALL-LABEL: cxb:
12+
13+
; ALL: addiu $[[T0:[0-9]+]], $zero, 10
14+
15+
; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 24
16+
; 32R1: sra $4, $[[T1]], 24
17+
18+
; 32R2: seb $4, $[[T0]]
19+
call void @xb(i8 10)
20+
ret void
21+
}
22+
23+
declare void @xh(i16)
24+
25+
define void @cxh() {
26+
; ALL-LABEL: cxh:
27+
28+
; ALL: addiu $[[T0:[0-9]+]], $zero, 10
29+
30+
; 32R1: sll $[[T1:[0-9]+]], $[[T0]], 16
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; 32R1: sra $4, $[[T1]], 16
32+
33+
; 32R2: seh $4, $[[T0]]
34+
call void @xh(i16 10)
35+
ret void
36+
}
37+
838
declare void @xi(i32)
939

1040
define void @cxi() {
@@ -17,6 +47,44 @@ define void @cxi() {
1747
ret void
1848
}
1949

50+
declare void @xbb(i8, i8)
51+
52+
define void @cxbb() {
53+
; ALL-LABEL: cxbb:
54+
55+
; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
56+
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
57+
58+
; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24
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; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
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; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
62+
63+
; 32R2-DAG: seb $4, $[[T0]]
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; 32R2-DAG: seb $5, $[[T1]]
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call void @xbb(i8 76, i8 101)
66+
ret void
67+
}
68+
69+
declare void @xhh(i16, i16)
70+
71+
define void @cxhh() {
72+
; ALL-LABEL: cxhh:
73+
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
75+
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
76+
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; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 16
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; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 16
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; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
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; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
81+
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; 32R2-DAG: seh $4, $[[T0]]
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; 32R2-DAG: seh $5, $[[T1]]
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call void @xhh(i16 76, i16 101)
85+
ret void
86+
}
87+
2088
declare void @xii(i32, i32)
2189

2290
define void @cxii() {
@@ -30,6 +98,52 @@ define void @cxii() {
3098
ret void
3199
}
32100

101+
declare void @xccc(i8, i8, i8)
102+
103+
define void @cxccc() {
104+
; ALL-LABEL: cxccc:
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; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
107+
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
108+
; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
109+
110+
; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 24
111+
; 32R1-DAG: sra $4, $[[T3]], 24
112+
; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
113+
; 32R1-DAG: sra $5, $[[T4]], 24
114+
; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 24
115+
; 32R1-DAG: sra $6, $[[T5]], 24
116+
117+
; 32R2-DAG: seb $4, $[[T0]]
118+
; 32R2-DAG: seb $5, $[[T1]]
119+
; 32R2-DAG: seb $6, $[[T2]]
120+
call void @xccc(i8 88, i8 44, i8 11)
121+
ret void
122+
}
123+
124+
declare void @xhhh(i16, i16, i16)
125+
126+
define void @cxhhh() {
127+
; ALL-LABEL: cxhhh:
128+
129+
; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
130+
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
131+
; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
132+
133+
; 32R1-DAG: sll $[[T3:[0-9]+]], $[[T0]], 16
134+
; 32R1-DAG: sra $4, $[[T3]], 16
135+
; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 16
136+
; 32R1-DAG: sra $5, $[[T4]], 16
137+
; 32R1-DAG: sll $[[T5:[0-9]+]], $[[T2]], 16
138+
; 32R1-DAG: sra $6, $[[T5]], 16
139+
140+
; 32R2-DAG: seh $4, $[[T0]]
141+
; 32R2-DAG: seh $5, $[[T1]]
142+
; 32R2-DAG: seh $6, $[[T2]]
143+
call void @xhhh(i16 88, i16 44, i16 11)
144+
ret void
145+
}
146+
33147
declare void @xiii(i32, i32, i32)
34148

35149
define void @cxiii() {
@@ -44,6 +158,76 @@ define void @cxiii() {
44158
ret void
45159
}
46160

161+
declare void @xcccc(i8, i8, i8, i8)
162+
163+
define void @cxcccc() {
164+
; ALL-LABEL: cxcccc:
165+
166+
; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
167+
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
168+
; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
169+
; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33
170+
171+
; FIXME: We should avoid the unnecessary spill/reload here.
172+
173+
; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 24
174+
; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
175+
; 32R1-DAG: sw $4, 16($sp)
176+
; 32R1-DAG: move $4, $[[T5]]
177+
; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 24
178+
; 32R1-DAG: sra $5, $[[T6]], 24
179+
; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 24
180+
; 32R1-DAG: sra $6, $[[T7]], 24
181+
; 32R1: lw $[[T8:[0-9]+]], 16($sp)
182+
; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 24
183+
; 32R1: sra $7, $[[T9]], 24
184+
185+
; 32R2-DAG: seb $[[T4:[0-9]+]], $[[T0]]
186+
; 32R2-DAG: sw $4, 16($sp)
187+
; 32R2-DAG: move $4, $[[T4]]
188+
; 32R2-DAG: seb $5, $[[T1]]
189+
; 32R2-DAG: seb $6, $[[T2]]
190+
; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
191+
; 32R2: seb $7, $[[T5]]
192+
call void @xcccc(i8 88, i8 44, i8 11, i8 33)
193+
ret void
194+
}
195+
196+
declare void @xhhhh(i16, i16, i16, i16)
197+
198+
define void @cxhhhh() {
199+
; ALL-LABEL: cxhhhh:
200+
201+
; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 88
202+
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 44
203+
; ALL-DAG: addiu $[[T2:[0-9]+]], $zero, 11
204+
; ALL-DAG: addiu $[[T3:[0-9]+]], $zero, 33
205+
206+
; FIXME: We should avoid the unnecessary spill/reload here.
207+
208+
; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T0]], 16
209+
; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 16
210+
; 32R1-DAG: sw $4, 16($sp)
211+
; 32R1-DAG: move $4, $[[T5]]
212+
; 32R1-DAG: sll $[[T6:[0-9]+]], $[[T1]], 16
213+
; 32R1-DAG: sra $5, $[[T6]], 16
214+
; 32R1-DAG: sll $[[T7:[0-9]+]], $[[T2]], 16
215+
; 32R1-DAG: sra $6, $[[T7]], 16
216+
; 32R1: lw $[[T8:[0-9]+]], 16($sp)
217+
; 32R1: sll $[[T9:[0-9]+]], $[[T8]], 16
218+
; 32R1: sra $7, $[[T9]], 16
219+
220+
; 32R2-DAG: seh $[[T4:[0-9]+]], $[[T0]]
221+
; 32R2-DAG: sw $4, 16($sp)
222+
; 32R2-DAG: move $4, $[[T4]]
223+
; 32R2-DAG: seh $5, $[[T1]]
224+
; 32R2-DAG: seh $6, $[[T2]]
225+
; 32R2-DAG: lw $[[T5:[0-9]+]], 16($sp)
226+
; 32R2: seh $7, $[[T5]]
227+
call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
228+
ret void
229+
}
230+
47231
declare void @xiiii(i32, i32, i32, i32)
48232

49233
define void @cxiiii() {

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