[mips][FastISel] Handle calls with non legal types i8 and i16.

[vkalintiris]

Summary

Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel.

Based on a patch by Reed Kotler.

Depends on D9635.

[dsanders]

Could you add a test case?

[dsanders]

My question was intended for the current owner of the revision (Vasileios) but I don't mind which of you creates the test case so long as there is one :-).

[vkalintiris]

Added tests for i8 and i16 arguments in function calls.

[dsanders]

LGTM with a nit

test/CodeGen/Mips/Fast-ISel/callabi.ll

11 ↗

(On Diff #25411)

Nit: Indentation

llvm/trunk/lib/Target/Mips/MipsFastISel.cpp

if (i == 0) {
       if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
         if (ArgVT == MVT::f32) {
           VA.convertToReg(Mips::F14);
         } else if (ArgVT == MVT::f64) {
           VA.convertToReg(Mips::D7);
         }
       }
     }
-    if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {
+    if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
+         (ArgVT == MVT::i8)) &&
+        VA.isMemLoc()) {
       switch (VA.getLocMemOffset()) {
       case 0:
         VA.convertToReg(Mips::A0);
         break;
       case 4:
         VA.convertToReg(Mips::A1);
         break;
       case 8:

llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll

 ; RUN: llc -march=mipsel -mcpu=mips32 -O0 \
 ; RUN:     -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
 ; RUN:     FileCheck %s -check-prefix=ALL -check-prefix=32R1
 ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \
 ; RUN:     -mips-fast-isel -relocation-model=pic -fast-isel-abort=1 < %s | \
 ; RUN:     FileCheck %s -check-prefix=ALL -check-prefix=32R2
 
+declare void @xb(i8)
+
+define void @cxb() {
+  ; ALL-LABEL:    cxb:
+
+  ; ALL:            addiu   $[[T0:[0-9]+]], $zero, 10
+
+  ; 32R1:           sll     $[[T1:[0-9]+]], $[[T0]], 24
+  ; 32R1:           sra     $4, $[[T1]], 24
+
+  ; 32R2:           seb     $4, $[[T0]]
+  call void @xb(i8 10)
+  ret void
+}
+
+declare void @xh(i16)
+
+define void @cxh() {
+  ; ALL-LABEL:    cxh:
+
+  ; ALL:            addiu   $[[T0:[0-9]+]], $zero, 10
+
+  ; 32R1:           sll     $[[T1:[0-9]+]], $[[T0]], 16
+  ; 32R1:           sra     $4, $[[T1]], 16
+
+  ; 32R2:           seh     $4, $[[T0]]
+  call void @xh(i16 10)
+  ret void
+}
+
 declare void @xi(i32)
 
 define void @cxi() {
   ; ALL-LABEL:    cxi:
 
   ; ALL-DAG:        addiu   $4, $zero, 10
   ; ALL-DAG:        lw      $25, %got(xi)(${{[0-9]+}})
   ; ALL:            jalr    $25
   call void @xi(i32 10)
   ret void
 }
 
+declare void @xbb(i8, i8)
+
+define void @cxbb() {
+  ; ALL-LABEL:    cxbb:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 76
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 101
+
+  ; 32R1-DAG:       sll     $[[T2:[0-9]+]], $[[T0]], 24
+  ; 32R1-DAG:       sra     $[[T3:[0-9]+]], $[[T2]], 24
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 24
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 24
+
+  ; 32R2-DAG:       seb     $4, $[[T0]]
+  ; 32R2-DAG:       seb     $5, $[[T1]]
+  call void @xbb(i8 76, i8 101)
+  ret void
+}
+
+declare void @xhh(i16, i16)
+
+define void @cxhh() {
+  ; ALL-LABEL:    cxhh:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 76
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 101
+
+  ; 32R1-DAG:       sll     $[[T2:[0-9]+]], $[[T0]], 16
+  ; 32R1-DAG:       sra     $[[T3:[0-9]+]], $[[T2]], 16
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 16
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 16
+
+  ; 32R2-DAG:       seh     $4, $[[T0]]
+  ; 32R2-DAG:       seh     $5, $[[T1]]
+  call void @xhh(i16 76, i16 101)
+  ret void
+}
+
 declare void @xii(i32, i32)
 
 define void @cxii() {
   ; ALL-LABEL:    cxii:
 
   ; ALL-DAG:        addiu   $4, $zero, 746
   ; ALL-DAG:        addiu   $5, $zero, 892
   ; ALL-DAG:        lw      $25, %got(xii)(${{[0-9]+}})
   ; ALL:            jalr    $25
   call void @xii(i32 746, i32 892)
   ret void
 }
 
+declare void @xccc(i8, i8, i8)
+
+define void @cxccc() {
+  ; ALL-LABEL:    cxccc:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
+
+  ; 32R1-DAG:       sll     $[[T3:[0-9]+]], $[[T0]], 24
+  ; 32R1-DAG:       sra     $4, $[[T3]], 24
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 24
+  ; 32R1-DAG:       sra     $5, $[[T4]], 24
+  ; 32R1-DAG:       sll     $[[T5:[0-9]+]], $[[T2]], 24
+  ; 32R1-DAG:       sra     $6, $[[T5]], 24
+
+  ; 32R2-DAG:       seb     $4, $[[T0]]
+  ; 32R2-DAG:       seb     $5, $[[T1]]
+  ; 32R2-DAG:       seb     $6, $[[T2]]
+  call void @xccc(i8 88, i8 44, i8 11)
+  ret void
+}
+
+declare void @xhhh(i16, i16, i16)
+
+define void @cxhhh() {
+  ; ALL-LABEL:    cxhhh:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
+
+  ; 32R1-DAG:       sll     $[[T3:[0-9]+]], $[[T0]], 16
+  ; 32R1-DAG:       sra     $4, $[[T3]], 16
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T1]], 16
+  ; 32R1-DAG:       sra     $5, $[[T4]], 16
+  ; 32R1-DAG:       sll     $[[T5:[0-9]+]], $[[T2]], 16
+  ; 32R1-DAG:       sra     $6, $[[T5]], 16
+
+  ; 32R2-DAG:       seh     $4, $[[T0]]
+  ; 32R2-DAG:       seh     $5, $[[T1]]
+  ; 32R2-DAG:       seh     $6, $[[T2]]
+  call void @xhhh(i16 88, i16 44, i16 11)
+  ret void
+}
+
 declare void @xiii(i32, i32, i32)
 
 define void @cxiii() {
   ; ALL-LABEL:    cxiii:
 
   ; ALL-DAG:        addiu   $4, $zero, 88
   ; ALL-DAG:        addiu   $5, $zero, 44
   ; ALL-DAG:        addiu   $6, $zero, 11
   ; ALL-DAG:        lw      $25, %got(xiii)(${{[0-9]+}})
   ; ALL:            jalr    $25
   call void @xiii(i32 88, i32 44, i32 11)
   ret void
 }
 
+declare void @xcccc(i8, i8, i8, i8)
+
+define void @cxcccc() {
+  ; ALL-LABEL:    cxcccc:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
+  ; ALL-DAG:        addiu   $[[T3:[0-9]+]], $zero, 33
+
+  ; FIXME: We should avoid the unnecessary spill/reload here.
+
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T0]], 24
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 24
+  ; 32R1-DAG:       sw      $4, 16($sp)
+  ; 32R1-DAG:       move    $4, $[[T5]]
+  ; 32R1-DAG:       sll     $[[T6:[0-9]+]], $[[T1]], 24
+  ; 32R1-DAG:       sra     $5, $[[T6]], 24
+  ; 32R1-DAG:       sll     $[[T7:[0-9]+]], $[[T2]], 24
+  ; 32R1-DAG:       sra     $6, $[[T7]], 24
+  ; 32R1:           lw      $[[T8:[0-9]+]], 16($sp)
+  ; 32R1:           sll     $[[T9:[0-9]+]], $[[T8]], 24
+  ; 32R1:           sra     $7, $[[T9]], 24
+
+  ; 32R2-DAG:       seb     $[[T4:[0-9]+]], $[[T0]]
+  ; 32R2-DAG:       sw      $4, 16($sp)
+  ; 32R2-DAG:       move    $4, $[[T4]]
+  ; 32R2-DAG:       seb     $5, $[[T1]]
+  ; 32R2-DAG:       seb     $6, $[[T2]]
+  ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
+  ; 32R2:           seb     $7, $[[T5]]
+  call void @xcccc(i8 88, i8 44, i8 11, i8 33)
+  ret void
+}
+
+declare void @xhhhh(i16, i16, i16, i16)
+
+define void @cxhhhh() {
+  ; ALL-LABEL:    cxhhhh:
+
+  ; ALL-DAG:        addiu   $[[T0:[0-9]+]], $zero, 88
+  ; ALL-DAG:        addiu   $[[T1:[0-9]+]], $zero, 44
+  ; ALL-DAG:        addiu   $[[T2:[0-9]+]], $zero, 11
+  ; ALL-DAG:        addiu   $[[T3:[0-9]+]], $zero, 33
+
+  ; FIXME: We should avoid the unnecessary spill/reload here.
+
+  ; 32R1-DAG:       sll     $[[T4:[0-9]+]], $[[T0]], 16
+  ; 32R1-DAG:       sra     $[[T5:[0-9]+]], $[[T4]], 16
+  ; 32R1-DAG:       sw      $4, 16($sp)
+  ; 32R1-DAG:       move    $4, $[[T5]]
+  ; 32R1-DAG:       sll     $[[T6:[0-9]+]], $[[T1]], 16
+  ; 32R1-DAG:       sra     $5, $[[T6]], 16
+  ; 32R1-DAG:       sll     $[[T7:[0-9]+]], $[[T2]], 16
+  ; 32R1-DAG:       sra     $6, $[[T7]], 16
+  ; 32R1:           lw      $[[T8:[0-9]+]], 16($sp)
+  ; 32R1:           sll     $[[T9:[0-9]+]], $[[T8]], 16
+  ; 32R1:           sra     $7, $[[T9]], 16
+
+  ; 32R2-DAG:       seh     $[[T4:[0-9]+]], $[[T0]]
+  ; 32R2-DAG:       sw      $4, 16($sp)
+  ; 32R2-DAG:       move    $4, $[[T4]]
+  ; 32R2-DAG:       seh     $5, $[[T1]]
+  ; 32R2-DAG:       seh     $6, $[[T2]]
+  ; 32R2-DAG:       lw      $[[T5:[0-9]+]], 16($sp)
+  ; 32R2:           seh     $7, $[[T5]]
+  call void @xhhhh(i16 88, i16 44, i16 11, i16 33)
+  ret void
+}
+
 declare void @xiiii(i32, i32, i32, i32)
 
 define void @cxiiii() {
   ; ALL-LABEL:    cxiiii:
 
   ; ALL-DAG:        addiu   $4, $zero, 167
   ; ALL-DAG:        addiu   $5, $zero, 320
   ; ALL-DAG:        addiu   $6, $zero, 97