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author
Toma Tabacu
committedAug 14, 2014
[mips] Improve robustness of some tests.
Summary: This is done by removing some hardcoded registers like $at or expecting a single digit register to be selected. Contains work done by Matheus Almeida. Reviewers: matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu Differential Revision: http://reviews.llvm.org/D4227 llvm-svn: 215640
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‎llvm/test/CodeGen/Mips/cconv/arguments-float.ll

+8-8
Original file line numberDiff line numberDiff line change
@@ -69,26 +69,26 @@ entry:
6969
; O32-DAG: sw [[R4]], 28([[R2]])
7070
; NEW-DAG: sd $6, 24([[R2]])
7171

72-
; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
73-
; O32-DAG: lw [[R4:\$[0-9]+]], 36($sp)
72+
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)
73+
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
7474
; O32-DAG: sw [[R3]], 32([[R2]])
7575
; O32-DAG: sw [[R4]], 36([[R2]])
7676
; NEW-DAG: sd $7, 32([[R2]])
7777

78-
; O32-DAG: lw [[R3:\$[0-9]+]], 40($sp)
79-
; O32-DAG: lw [[R4:\$[0-9]+]], 44($sp)
78+
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)
79+
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
8080
; O32-DAG: sw [[R3]], 40([[R2]])
8181
; O32-DAG: sw [[R4]], 44([[R2]])
8282
; NEW-DAG: sd $8, 40([[R2]])
8383

84-
; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp)
85-
; O32-DAG: lw [[R4:\$[0-9]+]], 52($sp)
84+
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)
85+
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)
8686
; O32-DAG: sw [[R3]], 48([[R2]])
8787
; O32-DAG: sw [[R4]], 52([[R2]])
8888
; NEW-DAG: sd $9, 48([[R2]])
8989

90-
; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp)
91-
; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp)
90+
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 56($sp)
91+
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 60($sp)
9292
; O32-DAG: sw [[R3]], 56([[R2]])
9393
; O32-DAG: sw [[R4]], 60([[R2]])
9494
; NEW-DAG: sd $10, 56([[R2]])

‎llvm/test/CodeGen/Mips/cconv/arguments.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ entry:
5353
; We won't test the way the global address is calculated in this test. This is
5454
; just to get the register number for the other checks.
5555
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
56-
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)(
56+
; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(
5757

5858
; The first four arguments are the same in O32/N32/N64
5959
; ALL-DAG: sb $4, 1([[R1]])
@@ -117,9 +117,9 @@ entry:
117117
; We won't test the way the global address is calculated in this test. This is
118118
; just to get the register number for the other checks.
119119
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
120-
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)(
120+
; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(
121121
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
122-
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(dwords)(
122+
; SYM64-DAG: ld [[R2:\$[0-9]+]], %got_disp(dwords)(
123123

124124
; The first argument is the same in O32/N32/N64.
125125
; ALL-DAG: sb $4, 1([[R1]])

‎llvm/test/CodeGen/Mips/cconv/return-float.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ entry:
3030
; O32-DAG: lw $2, %lo(float)([[R1]])
3131
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
3232
; N32-DAG: lw $2, %lo(float)([[R1]])
33-
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1)
33+
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)(
3434
; N64-DAG: lw $2, 0([[R1]])
3535

3636
define double @retdouble() nounwind {
@@ -44,5 +44,5 @@ entry:
4444
; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(double)
4545
; O32-DAG: lw $3, 4([[R2]])
4646
; N32-DAG: ld $2, %lo(double)([[R1:\$[0-9]+]])
47-
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1)
47+
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)(
4848
; N64-DAG: ld $2, 0([[R1]])

‎llvm/test/CodeGen/Mips/cconv/return-hard-float.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ entry:
3333
; O32-DAG: lwc1 $f0, %lo(float)([[R1]])
3434
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
3535
; N32-DAG: lwc1 $f0, %lo(float)([[R1]])
36-
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1)
36+
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)(
3737
; N64-DAG: lwc1 $f0, 0([[R1]])
3838

3939
define double @retdouble() nounwind {
@@ -45,7 +45,7 @@ entry:
4545
; ALL-LABEL: retdouble:
4646
; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
4747
; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
48-
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1)
48+
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)(
4949
; N64-DAG: ldc1 $f0, 0([[R1]])
5050

5151
define { double, double } @retComplexDouble() #0 {

‎llvm/test/CodeGen/Mips/cconv/return.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ entry:
3333
; O32-DAG: lbu $2, %lo(byte)([[R1]])
3434
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(byte)
3535
; N32-DAG: lbu $2, %lo(byte)([[R1]])
36-
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)($1)
36+
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)(
3737
; N64-DAG: lbu $2, 0([[R1]])
3838

3939
define i32 @reti32() nounwind {
@@ -47,7 +47,7 @@ entry:
4747
; O32-DAG: lw $2, %lo(word)([[R1]])
4848
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(word)
4949
; N32-DAG: lw $2, %lo(word)([[R1]])
50-
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)($1)
50+
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)(
5151
; N64-DAG: lw $2, 0([[R1]])
5252

5353
define i64 @reti64() nounwind {

‎llvm/test/CodeGen/Mips/msa/frameindex.ll

+46-46
Original file line numberDiff line numberDiff line change
@@ -36,10 +36,10 @@ define void @loadstore_v16i8_just_over_simm10() nounwind {
3636
%2 = alloca [497 x i8] ; Push the frame just over 512 bytes
3737

3838
%3 = load volatile <16 x i8>* %1
39-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512
39+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
4040
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
4141
store volatile <16 x i8> %3, <16 x i8>* %1
42-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512
42+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
4343
; MIPS32-AE: st.b [[R1]], 0([[BASE]])
4444

4545
ret void
@@ -53,12 +53,12 @@ define void @loadstore_v16i8_just_under_simm16() nounwind {
5353
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
5454

5555
%3 = load volatile <16 x i8>* %1
56-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
57-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
56+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
57+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
5858
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
5959
store volatile <16 x i8> %3, <16 x i8>* %1
60-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
61-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
60+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
61+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
6262
; MIPS32-AE: st.b [[R1]], 0([[BASE]])
6363

6464
ret void
@@ -72,12 +72,12 @@ define void @loadstore_v16i8_just_over_simm16() nounwind {
7272
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
7373

7474
%3 = load volatile <16 x i8>* %1
75-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
76-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
75+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
76+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
7777
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
7878
store volatile <16 x i8> %3, <16 x i8>* %1
79-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
80-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
79+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
80+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
8181
; MIPS32-AE: st.b [[R1]], 0([[BASE]])
8282

8383
ret void
@@ -107,10 +107,10 @@ define void @loadstore_v8i16_unaligned() nounwind {
107107
%5 = getelementptr [2 x <8 x i16>]* %4, i32 0, i32 0
108108

109109
%6 = load volatile <8 x i16>* %5
110-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
110+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
111111
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
112112
store volatile <8 x i16> %6, <8 x i16>* %5
113-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
113+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
114114
; MIPS32-AE: st.h [[R1]], 0([[BASE]])
115115

116116
ret void
@@ -139,10 +139,10 @@ define void @loadstore_v8i16_just_over_simm10() nounwind {
139139
%2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes
140140

141141
%3 = load volatile <8 x i16>* %1
142-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
142+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
143143
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
144144
store volatile <8 x i16> %3, <8 x i16>* %1
145-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024
145+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
146146
; MIPS32-AE: st.h [[R1]], 0([[BASE]])
147147

148148
ret void
@@ -156,12 +156,12 @@ define void @loadstore_v8i16_just_under_simm16() nounwind {
156156
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
157157

158158
%3 = load volatile <8 x i16>* %1
159-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
160-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
159+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
160+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
161161
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
162162
store volatile <8 x i16> %3, <8 x i16>* %1
163-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
164-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
163+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
164+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
165165
; MIPS32-AE: st.h [[R1]], 0([[BASE]])
166166

167167
ret void
@@ -175,12 +175,12 @@ define void @loadstore_v8i16_just_over_simm16() nounwind {
175175
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
176176

177177
%3 = load volatile <8 x i16>* %1
178-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
179-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
178+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
179+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
180180
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
181181
store volatile <8 x i16> %3, <8 x i16>* %1
182-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
183-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
182+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
183+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
184184
; MIPS32-AE: st.h [[R1]], 0([[BASE]])
185185

186186
ret void
@@ -210,10 +210,10 @@ define void @loadstore_v4i32_unaligned() nounwind {
210210
%5 = getelementptr [2 x <4 x i32>]* %4, i32 0, i32 0
211211

212212
%6 = load volatile <4 x i32>* %5
213-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
213+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
214214
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
215215
store volatile <4 x i32> %6, <4 x i32>* %5
216-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
216+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
217217
; MIPS32-AE: st.w [[R1]], 0([[BASE]])
218218

219219
ret void
@@ -242,10 +242,10 @@ define void @loadstore_v4i32_just_over_simm10() nounwind {
242242
%2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes
243243

244244
%3 = load volatile <4 x i32>* %1
245-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
245+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
246246
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
247247
store volatile <4 x i32> %3, <4 x i32>* %1
248-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048
248+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
249249
; MIPS32-AE: st.w [[R1]], 0([[BASE]])
250250

251251
ret void
@@ -259,12 +259,12 @@ define void @loadstore_v4i32_just_under_simm16() nounwind {
259259
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
260260

261261
%3 = load volatile <4 x i32>* %1
262-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
263-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
262+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
263+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
264264
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
265265
store volatile <4 x i32> %3, <4 x i32>* %1
266-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
267-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
266+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
267+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
268268
; MIPS32-AE: st.w [[R1]], 0([[BASE]])
269269

270270
ret void
@@ -278,12 +278,12 @@ define void @loadstore_v4i32_just_over_simm16() nounwind {
278278
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
279279

280280
%3 = load volatile <4 x i32>* %1
281-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
282-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
281+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
282+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
283283
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
284284
store volatile <4 x i32> %3, <4 x i32>* %1
285-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
286-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
285+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
286+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
287287
; MIPS32-AE: st.w [[R1]], 0([[BASE]])
288288

289289
ret void
@@ -313,10 +313,10 @@ define void @loadstore_v2i64_unaligned() nounwind {
313313
%5 = getelementptr [2 x <2 x i64>]* %4, i32 0, i32 0
314314

315315
%6 = load volatile <2 x i64>* %5
316-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
316+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
317317
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
318318
store volatile <2 x i64> %6, <2 x i64>* %5
319-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1
319+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
320320
; MIPS32-AE: st.d [[R1]], 0([[BASE]])
321321

322322
ret void
@@ -345,10 +345,10 @@ define void @loadstore_v2i64_just_over_simm10() nounwind {
345345
%2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes
346346

347347
%3 = load volatile <2 x i64>* %1
348-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
348+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
349349
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
350350
store volatile <2 x i64> %3, <2 x i64>* %1
351-
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096
351+
; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
352352
; MIPS32-AE: st.d [[R1]], 0([[BASE]])
353353

354354
ret void
@@ -362,12 +362,12 @@ define void @loadstore_v2i64_just_under_simm16() nounwind {
362362
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
363363

364364
%3 = load volatile <2 x i64>* %1
365-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
366-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
365+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
366+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
367367
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
368368
store volatile <2 x i64> %3, <2 x i64>* %1
369-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
370-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
369+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
370+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
371371
; MIPS32-AE: st.d [[R1]], 0([[BASE]])
372372

373373
ret void
@@ -381,12 +381,12 @@ define void @loadstore_v2i64_just_over_simm16() nounwind {
381381
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
382382

383383
%3 = load volatile <2 x i64>* %1
384-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
385-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
384+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
385+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
386386
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
387387
store volatile <2 x i64> %3, <2 x i64>* %1
388-
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768
389-
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]]
388+
; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
389+
; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
390390
; MIPS32-AE: st.d [[R1]], 0([[BASE]])
391391

392392
ret void

‎llvm/test/CodeGen/Mips/octeon_popcnt.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ define i8 @cnt8(i8 %x) nounwind readnone {
66
ret i8 %cnt
77
; OCTEON-LABEL: cnt8:
88
; OCTEON: jr $ra
9-
; OCTEON: pop $2, $1
9+
; OCTEON: pop $2, [[R1:\$[0-9]+]]
1010
; MIPS64-LABEL: cnt8:
1111
; MIPS64-NOT: pop
1212
}
@@ -16,7 +16,7 @@ define i16 @cnt16(i16 %x) nounwind readnone {
1616
ret i16 %cnt
1717
; OCTEON-LABEL: cnt16:
1818
; OCTEON: jr $ra
19-
; OCTEON: pop $2, $1
19+
; OCTEON: pop $2, [[R1:\$[0-9]+]]
2020
; MIPS64-LABEL: cnt16:
2121
; MIPS64-NOT: pop
2222
}

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