This is an archive of the discontinued LLVM Phabricator instance.

Differential D4227

[mips] Improve robustness of some tests.
ClosedPublic

Authored by tomatabacu on Jun 20 2014, 2:59 AM.

Details

Reviewers
dsanders
matheusalmeida
Commits
rG3f173e827a18: Merged from r215640:
rG726f1ea2c50b: [mips] Improve robustness of some tests.
rL223012: Merged from r215640:
rL215640: [mips] Improve robustness of some tests.
Summary

This is done by removing some hardcoded registers like $at or expecting a single digit register to be selected.

Contains work done by Matheus Almeida.

Diff Detail

Event Timeline

matheusalmeida updated this revision to Diff 10689.Jun 20 2014, 2:59 AM
matheusalmeida retitled this revision from to [mips] Improve robustness of some tests..
matheusalmeida updated this object.
matheusalmeida edited the test plan for this revision. (Show Details)
matheusalmeida added a reviewer: dsanders.Jun 20 2014, 3:02 AM

Adding you as a reviewer.

tomatabacu commandeered this revision.Aug 13 2014, 8:50 AM
tomatabacu added a reviewer: matheusalmeida.
tomatabacu added a subscriber: tomatabacu.

Commandeered to finish off the patch and make it ready for commit.

dsanders accepted this revision.Aug 14 2014, 1:47 AM
dsanders edited edge metadata.

LGTM

This revision is now accepted and ready to land.Aug 14 2014, 1:47 AM
tomatabacu updated this object.Aug 14 2014, 5:32 AM
tomatabacu edited edge metadata.
tomatabacu closed this revision.Aug 14 2014, 6:19 AM

Revision Contents

PathSize
test/
CodeGen/
Mips/
cconv/
16 lines
6 lines
4 lines
4 lines
4 lines
msa/
92 lines
4 lines

Diff 10689

test/CodeGen/Mips/cconv/arguments-float.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; O32 has run out of argument registers and starts using the stack ; O32 has run out of argument registers and starts using the stack
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp) ; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp)
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp) ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)
; O32-DAG: sw [[R3]], 24([[R2]]) ; O32-DAG: sw [[R3]], 24([[R2]])
; O32-DAG: sw [[R4]], 28([[R2]]) ; O32-DAG: sw [[R4]], 28([[R2]])
; NEW-DAG: sd $6, 24([[R2]]) ; NEW-DAG: sd $6, 24([[R2]])
; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp) ; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 36($sp) ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
; O32-DAG: sw [[R3]], 32([[R2]]) ; O32-DAG: sw [[R3]], 32([[R2]])
; O32-DAG: sw [[R4]], 36([[R2]]) ; O32-DAG: sw [[R4]], 36([[R2]])
; NEW-DAG: sd $7, 32([[R2]]) ; NEW-DAG: sd $7, 32([[R2]])
; O32-DAG: lw [[R3:\$[0-9]+]], 40($sp) ; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 44($sp) ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
; O32-DAG: sw [[R3]], 40([[R2]]) ; O32-DAG: sw [[R3]], 40([[R2]])
; O32-DAG: sw [[R4]], 44([[R2]]) ; O32-DAG: sw [[R4]], 44([[R2]])
; NEW-DAG: sd $8, 40([[R2]]) ; NEW-DAG: sd $8, 40([[R2]])
; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp) ; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 52($sp) ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)
; O32-DAG: sw [[R3]], 48([[R2]]) ; O32-DAG: sw [[R3]], 48([[R2]])
; O32-DAG: sw [[R4]], 52([[R2]]) ; O32-DAG: sw [[R4]], 52([[R2]])
; NEW-DAG: sd $9, 48([[R2]]) ; NEW-DAG: sd $9, 48([[R2]])
; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp) ; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 56($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp) ; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 60($sp)
; O32-DAG: sw [[R3]], 56([[R2]]) ; O32-DAG: sw [[R3]], 56([[R2]])
; O32-DAG: sw [[R4]], 60([[R2]]) ; O32-DAG: sw [[R4]], 60([[R2]])
; NEW-DAG: sd $10, 56([[R2]]) ; NEW-DAG: sd $10, 56([[R2]])
; N32/N64 have run out of registers and starts using the stack too ; N32/N64 have run out of registers and starts using the stack too
; O32-DAG: lw [[R3:\$[0-9]+]], 64($sp) ; O32-DAG: lw [[R3:\$[0-9]+]], 64($sp)
; O32-DAG: lw [[R4:\$[0-9]+]], 68($sp) ; O32-DAG: lw [[R4:\$[0-9]+]], 68($sp)
; O32-DAG: sw [[R3]], 64([[R2]]) ; O32-DAG: sw [[R3]], 64([[R2]])
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

test/CodeGen/Mips/cconv/arguments.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Linesentry:
store volatile i8 %j, i8* %9 store volatile i8 %j, i8* %9
ret void ret void
} }
; ALL-LABEL: align_to_arg_slots: ; ALL-LABEL: align_to_arg_slots:
; We won't test the way the global address is calculated in this test. This is ; We won't test the way the global address is calculated in this test. This is
; just to get the register number for the other checks. ; just to get the register number for the other checks.
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( ; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(
; The first four arguments are the same in O32/N32/N64 ; The first four arguments are the same in O32/N32/N64
; ALL-DAG: sb $4, 1([[R1]]) ; ALL-DAG: sb $4, 1([[R1]])
; ALL-DAG: sb $5, 2([[R1]]) ; ALL-DAG: sb $5, 2([[R1]])
; ALL-DAG: sb $6, 3([[R1]]) ; ALL-DAG: sb $6, 3([[R1]])
; ALL-DAG: sb $7, 4([[R1]]) ; ALL-DAG: sb $7, 4([[R1]])
; N32/N64 get an extra four arguments in registers ; N32/N64 get an extra four arguments in registers
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Linesentry:
store volatile i8 %j, i8* %8 store volatile i8 %j, i8* %8
ret void ret void
} }
; ALL-LABEL: slot_skipping: ; ALL-LABEL: slot_skipping:
; We won't test the way the global address is calculated in this test. This is ; We won't test the way the global address is calculated in this test. This is
; just to get the register number for the other checks. ; just to get the register number for the other checks.
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes) ; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
; SYM64-DAG: ld [[R1:\$[0-9]]], %got_disp(bytes)( ; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords) ; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; SYM64-DAG: ld [[R2:\$[0-9]]], %got_disp(dwords)( ; SYM64-DAG: ld [[R2:\$[0-9]+]], %got_disp(dwords)(
; The first argument is the same in O32/N32/N64. ; The first argument is the same in O32/N32/N64.
; ALL-DAG: sb $4, 1([[R1]]) ; ALL-DAG: sb $4, 1([[R1]])
; The second slot is insufficiently aligned for i64 on O32 so it is skipped. ; The second slot is insufficiently aligned for i64 on O32 so it is skipped.
; Also, i64 occupies two slots on O32 and only one for N32/N64. ; Also, i64 occupies two slots on O32 and only one for N32/N64.
; O32-DAG: sw $6, 8([[R2]]) ; O32-DAG: sw $6, 8([[R2]])
; O32-DAG: sw $7, 12([[R2]]) ; O32-DAG: sw $7, 12([[R2]])
Show All 40 Lines

test/CodeGen/Mips/cconv/return-float.ll

Show All 24 Linesentry:
ret float %0 ret float %0
} }
; ALL-LABEL: retfloat: ; ALL-LABEL: retfloat:
; O32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; O32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
; O32-DAG: lw $2, %lo(float)([[R1]]) ; O32-DAG: lw $2, %lo(float)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
; N32-DAG: lw $2, %lo(float)([[R1]]) ; N32-DAG: lw $2, %lo(float)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1) ; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)(
; N64-DAG: lw $2, 0([[R1]]) ; N64-DAG: lw $2, 0([[R1]])
define double @retdouble() nounwind { define double @retdouble() nounwind {
entry: entry:
%0 = load volatile double* @double %0 = load volatile double* @double
ret double %0 ret double %0
} }
; ALL-LABEL: retdouble: ; ALL-LABEL: retdouble:
; O32-DAG: lw $2, %lo(double)([[R1:\$[0-9]+]]) ; O32-DAG: lw $2, %lo(double)([[R1:\$[0-9]+]])
; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(double) ; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(double)
; O32-DAG: lw $3, 4([[R2]]) ; O32-DAG: lw $3, 4([[R2]])
; N32-DAG: ld $2, %lo(double)([[R1:\$[0-9]+]]) ; N32-DAG: ld $2, %lo(double)([[R1:\$[0-9]+]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1) ; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)(
; N64-DAG: ld $2, 0([[R1]]) ; N64-DAG: ld $2, 0([[R1]])

test/CodeGen/Mips/cconv/return-hard-float.ll

Show All 24 Linesentry:
ret float %0 ret float %0
} }
; ALL-LABEL: retfloat: ; ALL-LABEL: retfloat:
; O32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; O32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
; O32-DAG: lwc1 $f0, %lo(float)([[R1]]) ; O32-DAG: lwc1 $f0, %lo(float)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(float)
; N32-DAG: lwc1 $f0, %lo(float)([[R1]]) ; N32-DAG: lwc1 $f0, %lo(float)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)($1) ; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(float)(
; N64-DAG: lwc1 $f0, 0([[R1]]) ; N64-DAG: lwc1 $f0, 0([[R1]])
define double @retdouble() nounwind { define double @retdouble() nounwind {
entry: entry:
%0 = load volatile double* @double %0 = load volatile double* @double
ret double %0 ret double %0
} }
; ALL-LABEL: retdouble: ; ALL-LABEL: retdouble:
; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]]) ; O32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]]) ; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1) ; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)(
; N64-DAG: ldc1 $f0, 0([[R1]]) ; N64-DAG: ldc1 $f0, 0([[R1]])

test/CodeGen/Mips/cconv/return.ll

Show All 27 Linesentry:
ret i8 %0 ret i8 %0
} }
; ALL-LABEL: reti8: ; ALL-LABEL: reti8:
; O32-DAG: lui [[R1:\$[0-9]+]], %hi(byte) ; O32-DAG: lui [[R1:\$[0-9]+]], %hi(byte)
; O32-DAG: lbu $2, %lo(byte)([[R1]]) ; O32-DAG: lbu $2, %lo(byte)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(byte) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(byte)
; N32-DAG: lbu $2, %lo(byte)([[R1]]) ; N32-DAG: lbu $2, %lo(byte)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)($1) ; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(byte)(
; N64-DAG: lbu $2, 0([[R1]]) ; N64-DAG: lbu $2, 0([[R1]])
define i32 @reti32() nounwind { define i32 @reti32() nounwind {
entry: entry:
%0 = load volatile i32* @word %0 = load volatile i32* @word
ret i32 %0 ret i32 %0
} }
; ALL-LABEL: reti32: ; ALL-LABEL: reti32:
; O32-DAG: lui [[R1:\$[0-9]+]], %hi(word) ; O32-DAG: lui [[R1:\$[0-9]+]], %hi(word)
; O32-DAG: lw $2, %lo(word)([[R1]]) ; O32-DAG: lw $2, %lo(word)([[R1]])
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(word) ; N32-DAG: lui [[R1:\$[0-9]+]], %hi(word)
; N32-DAG: lw $2, %lo(word)([[R1]]) ; N32-DAG: lw $2, %lo(word)([[R1]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)($1) ; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(word)(
; N64-DAG: lw $2, 0([[R1]]) ; N64-DAG: lw $2, 0([[R1]])
define i64 @reti64() nounwind { define i64 @reti64() nounwind {
entry: entry:
%0 = load volatile i64* @dword %0 = load volatile i64* @dword
ret i64 %0 ret i64 %0
} }
; ALL-LABEL: reti64: ; ALL-LABEL: reti64:
; On O32, we must use v0 and v1 for the return value ; On O32, we must use v0 and v1 for the return value
; O32-DAG: lw $2, %lo(dword)([[R1:\$[0-9]+]]) ; O32-DAG: lw $2, %lo(dword)([[R1:\$[0-9]+]])
; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(dword) ; O32-DAG: addiu [[R2:\$[0-9]+]], [[R1]], %lo(dword)
; O32-DAG: lw $3, 4([[R2]]) ; O32-DAG: lw $3, 4([[R2]])
; N32-DAG: ld $2, %lo(dword)([[R1:\$[0-9]+]]) ; N32-DAG: ld $2, %lo(dword)([[R1:\$[0-9]+]])
; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(dword)([[R1:\$[0-9]+]]) ; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(dword)([[R1:\$[0-9]+]])
; N64-DAG: ld $2, 0([[R1]]) ; N64-DAG: ld $2, 0([[R1]])

test/CodeGen/Mips/msa/frameindex.ll

Show All 30 Lines
define void @loadstore_v16i8_just_over_simm10() nounwind { define void @loadstore_v16i8_just_over_simm10() nounwind {
; MIPS32-AE: loadstore_v16i8_just_over_simm10: ; MIPS32-AE: loadstore_v16i8_just_over_simm10:
%1 = alloca <16 x i8> %1 = alloca <16 x i8>
%2 = alloca [497 x i8] ; Push the frame just over 512 bytes %2 = alloca [497 x i8] ; Push the frame just over 512 bytes
%3 = load volatile <16 x i8>* %1 %3 = load volatile <16 x i8>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1 store volatile <16 x i8> %3, <16 x i8>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 512 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
; MIPS32-AE: st.b [[R1]], 0([[BASE]]) ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v16i8_just_over_simm10 ; MIPS32-AE: .size loadstore_v16i8_just_over_simm10
} }
define void @loadstore_v16i8_just_under_simm16() nounwind { define void @loadstore_v16i8_just_under_simm16() nounwind {
; MIPS32-AE: loadstore_v16i8_just_under_simm16: ; MIPS32-AE: loadstore_v16i8_just_under_simm16:
%1 = alloca <16 x i8> %1 = alloca <16 x i8>
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
%3 = load volatile <16 x i8>* %1 %3 = load volatile <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1 store volatile <16 x i8> %3, <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.b [[R1]], 0([[BASE]]) ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v16i8_just_under_simm16 ; MIPS32-AE: .size loadstore_v16i8_just_under_simm16
} }
define void @loadstore_v16i8_just_over_simm16() nounwind { define void @loadstore_v16i8_just_over_simm16() nounwind {
; MIPS32-AE: loadstore_v16i8_just_over_simm16: ; MIPS32-AE: loadstore_v16i8_just_over_simm16:
%1 = alloca <16 x i8> %1 = alloca <16 x i8>
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
%3 = load volatile <16 x i8>* %1 %3 = load volatile <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1 store volatile <16 x i8> %3, <16 x i8>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.b [[R1]], 0([[BASE]]) ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v16i8_just_over_simm16 ; MIPS32-AE: .size loadstore_v16i8_just_over_simm16
} }
define void @loadstore_v8i16_near() nounwind { define void @loadstore_v8i16_near() nounwind {
; MIPS32-AE: loadstore_v8i16_near: ; MIPS32-AE: loadstore_v8i16_near:
Show All 13 Linesdefine void @loadstore_v8i16_unaligned() nounwind {
%1 = alloca [2 x <8 x i16>] %1 = alloca [2 x <8 x i16>]
%2 = bitcast [2 x <8 x i16>]* %1 to i8* %2 = bitcast [2 x <8 x i16>]* %1 to i8*
%3 = getelementptr i8* %2, i32 1 %3 = getelementptr i8* %2, i32 1
%4 = bitcast i8* %3 to [2 x <8 x i16>]* %4 = bitcast i8* %3 to [2 x <8 x i16>]*
%5 = getelementptr [2 x <8 x i16>]* %4, i32 0, i32 0 %5 = getelementptr [2 x <8 x i16>]* %4, i32 0, i32 0
%6 = load volatile <8 x i16>* %5 %6 = load volatile <8 x i16>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %6, <8 x i16>* %5 store volatile <8 x i16> %6, <8 x i16>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v8i16_unaligned ; MIPS32-AE: .size loadstore_v8i16_unaligned
} }
define void @loadstore_v8i16_just_under_simm10() nounwind { define void @loadstore_v8i16_just_under_simm10() nounwind {
; MIPS32-AE: loadstore_v8i16_just_under_simm10: ; MIPS32-AE: loadstore_v8i16_just_under_simm10:
Show All 12 Lines
define void @loadstore_v8i16_just_over_simm10() nounwind { define void @loadstore_v8i16_just_over_simm10() nounwind {
; MIPS32-AE: loadstore_v8i16_just_over_simm10: ; MIPS32-AE: loadstore_v8i16_just_over_simm10:
%1 = alloca <8 x i16> %1 = alloca <8 x i16>
%2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes %2 = alloca [1009 x i8] ; Push the frame just over 1024 bytes
%3 = load volatile <8 x i16>* %1 %3 = load volatile <8 x i16>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1 store volatile <8 x i16> %3, <8 x i16>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1024 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v8i16_just_over_simm10 ; MIPS32-AE: .size loadstore_v8i16_just_over_simm10
} }
define void @loadstore_v8i16_just_under_simm16() nounwind { define void @loadstore_v8i16_just_under_simm16() nounwind {
; MIPS32-AE: loadstore_v8i16_just_under_simm16: ; MIPS32-AE: loadstore_v8i16_just_under_simm16:
%1 = alloca <8 x i16> %1 = alloca <8 x i16>
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
%3 = load volatile <8 x i16>* %1 %3 = load volatile <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1 store volatile <8 x i16> %3, <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v8i16_just_under_simm16 ; MIPS32-AE: .size loadstore_v8i16_just_under_simm16
} }
define void @loadstore_v8i16_just_over_simm16() nounwind { define void @loadstore_v8i16_just_over_simm16() nounwind {
; MIPS32-AE: loadstore_v8i16_just_over_simm16: ; MIPS32-AE: loadstore_v8i16_just_over_simm16:
%1 = alloca <8 x i16> %1 = alloca <8 x i16>
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
%3 = load volatile <8 x i16>* %1 %3 = load volatile <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1 store volatile <8 x i16> %3, <8 x i16>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.h [[R1]], 0([[BASE]]) ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v8i16_just_over_simm16 ; MIPS32-AE: .size loadstore_v8i16_just_over_simm16
} }
define void @loadstore_v4i32_near() nounwind { define void @loadstore_v4i32_near() nounwind {
; MIPS32-AE: loadstore_v4i32_near: ; MIPS32-AE: loadstore_v4i32_near:
Show All 13 Linesdefine void @loadstore_v4i32_unaligned() nounwind {
%1 = alloca [2 x <4 x i32>] %1 = alloca [2 x <4 x i32>]
%2 = bitcast [2 x <4 x i32>]* %1 to i8* %2 = bitcast [2 x <4 x i32>]* %1 to i8*
%3 = getelementptr i8* %2, i32 1 %3 = getelementptr i8* %2, i32 1
%4 = bitcast i8* %3 to [2 x <4 x i32>]* %4 = bitcast i8* %3 to [2 x <4 x i32>]*
%5 = getelementptr [2 x <4 x i32>]* %4, i32 0, i32 0 %5 = getelementptr [2 x <4 x i32>]* %4, i32 0, i32 0
%6 = load volatile <4 x i32>* %5 %6 = load volatile <4 x i32>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %6, <4 x i32>* %5 store volatile <4 x i32> %6, <4 x i32>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v4i32_unaligned ; MIPS32-AE: .size loadstore_v4i32_unaligned
} }
define void @loadstore_v4i32_just_under_simm10() nounwind { define void @loadstore_v4i32_just_under_simm10() nounwind {
; MIPS32-AE: loadstore_v4i32_just_under_simm10: ; MIPS32-AE: loadstore_v4i32_just_under_simm10:
Show All 12 Lines
define void @loadstore_v4i32_just_over_simm10() nounwind { define void @loadstore_v4i32_just_over_simm10() nounwind {
; MIPS32-AE: loadstore_v4i32_just_over_simm10: ; MIPS32-AE: loadstore_v4i32_just_over_simm10:
%1 = alloca <4 x i32> %1 = alloca <4 x i32>
%2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes %2 = alloca [2033 x i8] ; Push the frame just over 2048 bytes
%3 = load volatile <4 x i32>* %1 %3 = load volatile <4 x i32>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1 store volatile <4 x i32> %3, <4 x i32>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 2048 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v4i32_just_over_simm10 ; MIPS32-AE: .size loadstore_v4i32_just_over_simm10
} }
define void @loadstore_v4i32_just_under_simm16() nounwind { define void @loadstore_v4i32_just_under_simm16() nounwind {
; MIPS32-AE: loadstore_v4i32_just_under_simm16: ; MIPS32-AE: loadstore_v4i32_just_under_simm16:
%1 = alloca <4 x i32> %1 = alloca <4 x i32>
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
%3 = load volatile <4 x i32>* %1 %3 = load volatile <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1 store volatile <4 x i32> %3, <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v4i32_just_under_simm16 ; MIPS32-AE: .size loadstore_v4i32_just_under_simm16
} }
define void @loadstore_v4i32_just_over_simm16() nounwind { define void @loadstore_v4i32_just_over_simm16() nounwind {
; MIPS32-AE: loadstore_v4i32_just_over_simm16: ; MIPS32-AE: loadstore_v4i32_just_over_simm16:
%1 = alloca <4 x i32> %1 = alloca <4 x i32>
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
%3 = load volatile <4 x i32>* %1 %3 = load volatile <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1 store volatile <4 x i32> %3, <4 x i32>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.w [[R1]], 0([[BASE]]) ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v4i32_just_over_simm16 ; MIPS32-AE: .size loadstore_v4i32_just_over_simm16
} }
define void @loadstore_v2i64_near() nounwind { define void @loadstore_v2i64_near() nounwind {
; MIPS32-AE: loadstore_v2i64_near: ; MIPS32-AE: loadstore_v2i64_near:
Show All 13 Linesdefine void @loadstore_v2i64_unaligned() nounwind {
%1 = alloca [2 x <2 x i64>] %1 = alloca [2 x <2 x i64>]
%2 = bitcast [2 x <2 x i64>]* %1 to i8* %2 = bitcast [2 x <2 x i64>]* %1 to i8*
%3 = getelementptr i8* %2, i32 1 %3 = getelementptr i8* %2, i32 1
%4 = bitcast i8* %3 to [2 x <2 x i64>]* %4 = bitcast i8* %3 to [2 x <2 x i64>]*
%5 = getelementptr [2 x <2 x i64>]* %4, i32 0, i32 0 %5 = getelementptr [2 x <2 x i64>]* %4, i32 0, i32 0
%6 = load volatile <2 x i64>* %5 %6 = load volatile <2 x i64>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %6, <2 x i64>* %5 store volatile <2 x i64> %6, <2 x i64>* %5
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 1 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v2i64_unaligned ; MIPS32-AE: .size loadstore_v2i64_unaligned
} }
define void @loadstore_v2i64_just_under_simm10() nounwind { define void @loadstore_v2i64_just_under_simm10() nounwind {
; MIPS32-AE: loadstore_v2i64_just_under_simm10: ; MIPS32-AE: loadstore_v2i64_just_under_simm10:
Show All 12 Lines
define void @loadstore_v2i64_just_over_simm10() nounwind { define void @loadstore_v2i64_just_over_simm10() nounwind {
; MIPS32-AE: loadstore_v2i64_just_over_simm10: ; MIPS32-AE: loadstore_v2i64_just_over_simm10:
%1 = alloca <2 x i64> %1 = alloca <2 x i64>
%2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes %2 = alloca [4081 x i8] ; Push the frame just over 4096 bytes
%3 = load volatile <2 x i64>* %1 %3 = load volatile <2 x i64>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1 store volatile <2 x i64> %3, <2 x i64>* %1
; MIPS32-AE: addiu [[BASE:\$[0-9]+]], $sp, 4096 ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v2i64_just_over_simm10 ; MIPS32-AE: .size loadstore_v2i64_just_over_simm10
} }
define void @loadstore_v2i64_just_under_simm16() nounwind { define void @loadstore_v2i64_just_under_simm16() nounwind {
; MIPS32-AE: loadstore_v2i64_just_under_simm16: ; MIPS32-AE: loadstore_v2i64_just_under_simm16:
%1 = alloca <2 x i64> %1 = alloca <2 x i64>
%2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes %2 = alloca [32752 x i8] ; Push the frame right up to 32768 bytes
%3 = load volatile <2 x i64>* %1 %3 = load volatile <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1 store volatile <2 x i64> %3, <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v2i64_just_under_simm16 ; MIPS32-AE: .size loadstore_v2i64_just_under_simm16
} }
define void @loadstore_v2i64_just_over_simm16() nounwind { define void @loadstore_v2i64_just_over_simm16() nounwind {
; MIPS32-AE: loadstore_v2i64_just_over_simm16: ; MIPS32-AE: loadstore_v2i64_just_over_simm16:
%1 = alloca <2 x i64> %1 = alloca <2 x i64>
%2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes %2 = alloca [32753 x i8] ; Push the frame just over 32768 bytes
%3 = load volatile <2 x i64>* %1 %3 = load volatile <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]]) ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1 store volatile <2 x i64> %3, <2 x i64>* %1
; MIPS32-AE: ori [[R2:\$[0-9]+]], $zero, 32768 ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
; MIPS32-AE: addu [[BASE:\$[0-9]+]], $sp, [[R2]] ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
; MIPS32-AE: st.d [[R1]], 0([[BASE]]) ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
ret void ret void
; MIPS32-AE: .size loadstore_v2i64_just_over_simm16 ; MIPS32-AE: .size loadstore_v2i64_just_over_simm16
} }

test/CodeGen/Mips/octeon_popcnt.ll

; RUN: llc -O1 -march=mips64 -mcpu=octeon < %s | FileCheck %s -check-prefix=OCTEON ; RUN: llc -O1 -march=mips64 -mcpu=octeon < %s | FileCheck %s -check-prefix=OCTEON
; RUN: llc -O1 -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64 ; RUN: llc -O1 -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=MIPS64
define i8 @cnt8(i8 %x) nounwind readnone { define i8 @cnt8(i8 %x) nounwind readnone {
%cnt = tail call i8 @llvm.ctpop.i8(i8 %x) %cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
ret i8 %cnt ret i8 %cnt
; OCTEON-LABEL: cnt8: ; OCTEON-LABEL: cnt8:
; OCTEON: jr $ra ; OCTEON: jr $ra
; OCTEON: pop $2, $1 ; OCTEON: pop $2, [[R1:\$[0-9]+]]
; MIPS64-LABEL: cnt8: ; MIPS64-LABEL: cnt8:
; MIPS64-NOT: pop ; MIPS64-NOT: pop
} }
define i16 @cnt16(i16 %x) nounwind readnone { define i16 @cnt16(i16 %x) nounwind readnone {
%cnt = tail call i16 @llvm.ctpop.i16(i16 %x) %cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
ret i16 %cnt ret i16 %cnt
; OCTEON-LABEL: cnt16: ; OCTEON-LABEL: cnt16:
; OCTEON: jr $ra ; OCTEON: jr $ra
; OCTEON: pop $2, $1 ; OCTEON: pop $2, [[R1:\$[0-9]+]]
; MIPS64-LABEL: cnt16: ; MIPS64-LABEL: cnt16:
; MIPS64-NOT: pop ; MIPS64-NOT: pop
} }
define i32 @cnt32(i32 %x) nounwind readnone { define i32 @cnt32(i32 %x) nounwind readnone {
%cnt = tail call i32 @llvm.ctpop.i32(i32 %x) %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %cnt ret i32 %cnt
; OCTEON-LABEL: cnt32: ; OCTEON-LABEL: cnt32:
Show All 20 Lines