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Differential D8753

Sparc: Prefer reg+reg address encoding when only one register used.
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Authored by jyknight on Mar 31 2015, 3:14 PM.

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Reviewers
venkatra
Commits
rGc09bdfa4cbfd: Sparc: Prefer reg+reg address encoding when only one register used.
rL236107: Sparc: Prefer reg+reg address encoding when only one register used.
Summary

Reg+%g0 is preferred to Reg+imm0 by the manual, and is what GCC produces.

Futhermore, reg+imm is invalid for the (not yet supported) "alternate address space" instructions.

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rL LLVM

Event Timeline

jyknight updated this revision to Diff 23011.Mar 31 2015, 3:14 PM
jyknight retitled this revision from to Sparc: Prefer reg+reg address encoding when only one register used..
jyknight updated this object.
jyknight edited the test plan for this revision. (Show Details)
jyknight set the repository for this revision to rL LLVM.
jyknight added a subscriber: Unknown Object (MLST).
jyknight added a subscriber: venkatra.Apr 2 2015, 8:20 AM
jyknight updated this revision to Diff 23417.Apr 8 2015, 7:40 AM
jyknight updated this object.

(No real changes; just rebased to not be on top of the LDD/STD patch)

jyknight added a reviewer: venkatra.Apr 27 2015, 10:23 AM

Ping

venkatra accepted this revision.Apr 28 2015, 7:27 PM
venkatra edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Apr 28 2015, 7:27 PM
Closed by commit rL236107: Sparc: Prefer reg+reg address encoding when only one register used. (authored by jyknight). · Explain WhyApr 29 2015, 7:58 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents
Changeset List

PathSize
llvm/
trunk/
lib/
Target/
Sparc/
AsmParser/
10 lines
test/
MC/
Disassembler/
Sparc/
54 lines
Sparc/
6 lines
16 lines

Diff 24633

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llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp

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llvm/trunk/test/MC/Disassembler/Sparc/sparc-mem.txt

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llvm/trunk/test/MC/Sparc/sparc-ctrl-instructions.s

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llvm/trunk/test/MC/Sparc/sparc-mem-instructions.s

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