Non-8-bit addressable units showcase

[JesperAntonsson]

Summary

This is a twin patch to D61432, using the "addressable units" terminology instead of "byte".

It's meant to be an addition to llvm-dev discussion "RFC: On removing magic numbers assuming 8-bit bytes", just to show one way it could look when using "addressable unit" terminology.

[• Tommy]

Dear Jesper,

I am working on an architecture where the minimal addressable unit size is 64 bit. So far everything worked fine until I started testing strings(i8-layout) and pointer to char and short, were I ran into serious problems with the 8-bit/Byte alignment philosophy of LLVM. After research with Dr. Google I found a solution from Embecosm and your approach and decided to follow this solution.

My question is:

How do you deal with the Int8PtrTy, AllocaInt8PtrTy and getInt8PtrTy, which are all over llvm and clang.
e.g.

Int8PtrTy = Int8Ty->getPointerTo(0);
Int8PtrPtrTy = Int8PtrTy->getPointerTo(0);
AllocaInt8PtrTy = Int8Ty->getPointerTo(
    M.getDataLayout().getAllocaAddrSpace());

or

Int8Ptr(Type::getInt8PtrTy(Context)),
ResumeFnType(FunctionType::get(Type::getVoidTy(Context), Int8Ptr,
                               /*isVarArg=*/false)),
NullPtr(ConstantPointerNull::get(Int8Ptr)) {}

or

/// void* in address space 0
union {
  llvm::PointerType *VoidPtrTy;
  llvm::PointerType *Int8PtrTy;
};

I would appreciate your help ([e-mail])

Thomas

include/llvm/IR/DataLayout.h

enum class FunctionPtrAlignType {
     Independent,
     /// The function pointer alignment is a multiple of the function alignment.
     MultipleOfFunctionAlign,
   };
 private:
   /// Defaults to false.
   bool BigEndian;
 
+  /// Smallest number of bits in an addressable unit. Defaults to 8.
+  unsigned BitsPerAddressableUnit;
+
   unsigned AllocaAddrSpace;
   unsigned StackNaturalAlign;
   unsigned ProgramAddrSpace;
 
   unsigned FunctionPtrAlign;
   FunctionPtrAlignType TheFunctionPtrAlignType;
 
   enum ManglingModeT {
DataLayout &operator=(const DataLayout &DL) {
     clear();
     StringRepresentation = DL.StringRepresentation;
     BigEndian = DL.isBigEndian();
     AllocaAddrSpace = DL.AllocaAddrSpace;
     StackNaturalAlign = DL.StackNaturalAlign;
     FunctionPtrAlign = DL.FunctionPtrAlign;
     TheFunctionPtrAlignType = DL.TheFunctionPtrAlignType;
     ProgramAddrSpace = DL.ProgramAddrSpace;
+    BitsPerAddressableUnit = DL.BitsPerAddressableUnit;
     ManglingMode = DL.ManglingMode;
     LegalIntWidths = DL.LegalIntWidths;
     Alignments = DL.Alignments;
     Pointers = DL.Pointers;
     NonIntegralAddressSpaces = DL.NonIntegralAddressSpaces;
     return *this;
   }
 
   bool operator==(const DataLayout &Other) const;
   bool operator!=(const DataLayout &Other) const { return !(*this == Other); }
 
   void init(const Module *M);
 
   /// Parse a data layout string (with fallback to default values).
   void reset(StringRef LayoutDescription);
 
   /// Layout endianness...
   bool isLittleEndian() const { return !BigEndian; }
   bool isBigEndian() const { return BigEndian; }
 
+  /// Returns the smallest number of bits per addressable unit for the target.
+  unsigned getBitsPerAU() const { return BitsPerAddressableUnit; }
+
   /// Returns the string representation of the DataLayout.
   ///
   /// This representation is in the same format accepted by the string
   /// constructor above. This should not be used to compare two DataLayout as
   /// different string can represent the same layout.
   const std::string &getStringRepresentation() const {
     return StringRepresentation;
   }
public:
   /// vector of pointers.
   unsigned getPointerTypeSizeInBits(Type *) const;
 
   /// Layout size of the index used in GEP calculation.
   /// The function should be called with pointer or vector of pointers type.
   unsigned getIndexTypeSizeInBits(Type *Ty) const;
 
   unsigned getPointerTypeSize(Type *Ty) const {
-    return getPointerTypeSizeInBits(Ty) / 8;
+    return getPointerTypeSizeInBits(Ty) / BitsPerAddressableUnit;
   }
 
   /// Size examples:
   ///
   /// Type        SizeInBits  StoreSizeInBits  AllocSizeInBits[*]
   /// ----        ----------  ---------------  ---------------
   ///  i1            1           8                8
   ///  i8            8           8                8

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
           MaximumLegalStoreInBits = VT.getSizeInBits();
     }
 
     void ConsiderForPruning(SDNode *N) {
       // Mark this for potential pruning.
       PruningList.insert(N);
     }
 
+    /// Return number of bits per addressable unit.
+    LLVM_READONLY unsigned bitsPerAU() const {
+      return DAG.getDataLayout().getBitsPerAU();
+    }
+
+    /// Return minimum number of addressable units needed to store \p Bits.
+    LLVM_READONLY unsigned inAUs(unsigned Bits) const {
+      return (Bits + bitsPerAU() - 1) / bitsPerAU();
+    }
+
     /// Add to the worklist making sure its instance is at the back (next to be
     /// processed.)
     void AddToWorklist(SDNode *N) {
       assert(N->getOpcode() != ISD::DELETED_NODE &&
              "Deleted Node added to Worklist");
 
       // Skip handle nodes as they can't usefully be combined and confuse the
       // zero-use deletion strategy.

 }
 
 bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
                                     ISD::LoadExtType ExtType, EVT &MemVT,
                                     unsigned ShAmt) {
   if (!LDST)
     return false;
   // Only allow byte offsets.
-  if (ShAmt % 8)
+  if (ShAmt % bitsPerAU())
     return false;
 
   // Do not generate loads of non-round integer types since these can
   // be expensive (and would be wrong if the type is not byte sized).
   if (!MemVT.isRound())
     return false;
 
   // Don't change the width of a volatile load.
   if (LDST->isVolatile())
     return false;
 
   // Verify that we are actually reducing a load width here.
   if (LDST->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits())
     return false;
 
   // Ensure that this isn't going to produce an unsupported unaligned access.
   if (ShAmt &&
       !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
-                              LDST->getAddressSpace(), ShAmt / 8))
+                              LDST->getAddressSpace(), ShAmt / bitsPerAU()))
     return false;
 
   // It's not possible to generate a constant of extended or untyped type.
   EVT PtrType = LDST->getBasePtr().getValueType();
   if (PtrType == MVT::Untyped || PtrType.isExtended())
     return false;
 
   if (isa<LoadSDNode>(LDST)) {
SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
   };
 
   // For big endian targets, we need to adjust the offset to the pointer to
   // load the correct bytes.
   if (DAG.getDataLayout().isBigEndian())
     ShAmt = AdjustBigEndianShift(ShAmt);
 
   EVT PtrType = N0.getOperand(1).getValueType();
-  uint64_t PtrOff = ShAmt / 8;
+  uint64_t PtrOff = ShAmt / bitsPerAU();
   unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
   SDLoc DL(LN0);
   // The original load itself didn't wrap, so an offset within it doesn't.
   SDNodeFlags Flags;
   Flags.setNoUnsignedWrap(true);
   SDValue NewPtr = DAG.getNode(ISD::ADD, DL,
                                PtrType, LN0->getBasePtr(),
                                DAG.getConstant(PtrOff, DL, PtrType),
if (!BasePtrST.equalBaseIndex(BasePtrLD, DAG, Offset))
     return SDValue();
 
   // Normalize for Endianness. After this Offset=0 will denote that the least
   // significant bit in the loaded value maps to the least significant bit in
   // the stored value). With Offset=n (for n > 0) the loaded value starts at the
   // n:th least significant byte of the stored value.
   if (DAG.getDataLayout().isBigEndian())
     Offset = (STMemType.getStoreSizeInBits() -
-              LDMemType.getStoreSizeInBits()) / 8 - Offset;
+              LDMemType.getStoreSizeInBits()) / bitsPerAU() - Offset;
 
   // Check that the stored value cover all bits that are loaded.
   bool STCoversLD =
       (Offset >= 0) &&
-      (Offset * 8 + LDMemType.getSizeInBits() <= STMemType.getSizeInBits());
+      (Offset * bitsPerAU() + LDMemType.getSizeInBits() <= STMemType.getSizeInBits());
 
   auto ReplaceLd = [&](LoadSDNode *LD, SDValue Val, SDValue Chain) -> SDValue {
     if (LD->isIndexed()) {
       bool IsSub = (LD->getAddressingMode() == ISD::PRE_DEC ||
                     LD->getAddressingMode() == ISD::POST_DEC);
       unsigned Opc = IsSub ? ISD::SUB : ISD::ADD;
       SDValue Idx = DAG.getNode(Opc, SDLoc(LD), LD->getOperand(1).getValueType(),
                              LD->getOperand(1), LD->getOperand(2));
struct LoadedSlice {
   // The DAG from which Origin came from.
   // This is used to get some contextual information about legal types, etc.
   SelectionDAG *DAG;
 
   LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
               unsigned Shift = 0, SelectionDAG *DAG = nullptr)
       : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
 
+  /// Return number of bits per addressable unit.
+  LLVM_READONLY unsigned bitsPerAU() const {
+    assert(DAG && "SelectionDAG not set.");
+    return DAG->getDataLayout().getBitsPerAU();
+  }
+
   /// Get the bits used in a chunk of bits \p BitWidth large.
   /// \return Result is \p BitWidth and has used bits set to 1 and
   ///         not used bits set to 0.
   APInt getUsedBits() const {
     // Reproduce the trunc(lshr) sequence:
     // - Start from the truncated value.
     // - Zero extend to the desired bit width.
     // - Shift left.
     assert(Origin && "No original load to compare against.");
     unsigned BitWidth = Origin->getValueSizeInBits(0);
     assert(Inst && "This slice is not bound to an instruction");
     assert(Inst->getValueSizeInBits(0) <= BitWidth &&
            "Extracted slice is bigger than the whole type!");
     APInt UsedBits(Inst->getValueSizeInBits(0), 0);
     UsedBits.setAllBits();
     UsedBits = UsedBits.zext(BitWidth);
     UsedBits <<= Shift;
     return UsedBits;
   }
 
   /// Get the size of the slice to be loaded in bytes.
   unsigned getLoadedSize() const {
     unsigned SliceSize = getUsedBits().countPopulation();
-    assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
-    return SliceSize / 8;
+    assert(SliceSize % bitsPerAU() == 0 &&
+           "Size is not a multiple of an addressable unit.");
+    return SliceSize / bitsPerAU();
   }
 
   /// Get the type that will be loaded for this slice.
   /// Note: This may not be the final type for the slice.
   EVT getLoadedType() const {
     assert(DAG && "Missing context");
     LLVMContext &Ctxt = *DAG->getContext();
-    return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
+    return EVT::getIntegerVT(Ctxt, getLoadedSize() * bitsPerAU());
   }
 
   /// Get the alignment of the load used for this slice.
   unsigned getAlignment() const {
     unsigned Alignment = Origin->getAlignment();
     unsigned Offset = getOffsetFromBase();
     if (Offset != 0)
       Alignment = MinAlign(Alignment, Alignment + Offset);
bool isLegal() const {
     return true;
   }
 
   /// Get the offset in bytes of this slice in the original chunk of
   /// bits.
   /// \pre DAG != nullptr.
   uint64_t getOffsetFromBase() const {
     assert(DAG && "Missing context.");
-    bool IsBigEndian = DAG->getDataLayout().isBigEndian();
-    assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
-    uint64_t Offset = Shift / 8;
-    unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
-    assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
-           "The size of the original loaded type is not a multiple of a"
-           " byte.");
+    const DataLayout &TD = DAG->getDataLayout();
+    bool IsBigEndian = TD.isBigEndian();
+    unsigned BitsPerAU = TD.getBitsPerAU();
+    assert(Shift % BitsPerAU == 0 &&
+           "Shifts not aligned on addressable units are not supported.");
+    uint64_t Offset = Shift / BitsPerAU;
+    unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / BitsPerAU;
+    assert(Origin->getValueSizeInBits(0) % BitsPerAU == 0 &&
+           "The size of the original loaded type is not a multiple of an"
+           " addressable unit.");
     // If Offset is bigger than TySizeInBytes, it means we are loading all
     // zeros. This should have been optimized before in the process.
     assert(TySizeInBytes > Offset &&
            "Invalid shift amount for given loaded size");
     if (IsBigEndian)
       Offset = TySizeInBytes - Offset - getLoadedSize();
     return Offset;
   }
for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
 
     // At this point, User is a Truncate, iff we encountered, trunc or
     // trunc(lshr).
     if (User->getOpcode() != ISD::TRUNCATE)
       return false;
 
     // The width of the type must be a power of 2 and greater than 8-bits.
     // Otherwise the load cannot be represented in LLVM IR.
-    // Moreover, if we shifted with a non-8-bits multiple, the slice
+    // Moreover, if we shifted with a non-bitsPerAU multiple, the slice
     // will be across several bytes. We do not support that.
     unsigned Width = User->getValueSizeInBits(0);
-    if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
+    if (Width < 8 || !isPowerOf2_32(Width) || (Shift % bitsPerAU()))
       return false;
 
     // Build the slice for this chain of computations.
     LoadedSlice LS(User, LD, Shift, &DAG);
     APInt CurrentUsedBits = LS.getUsedBits();
 
     // Check if this slice overlaps with another.
     if ((CurrentUsedBits & UsedBits) != 0)

 /// truncated IVal.
 static SDNode *
 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
                                 SDValue IVal, StoreSDNode *St,
                                 DAGCombiner *DC) {
   unsigned NumBytes = MaskInfo.first;
   unsigned ByteShift = MaskInfo.second;
   SelectionDAG &DAG = DC->getDAG();
+  unsigned BitsPerAU = DC->bitsPerAU();
 
   // Check to see if IVal is all zeros in the part being masked in by the 'or'
   // that uses this.  If not, this is not a replacement.
   APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
-                                  ByteShift*8, (ByteShift+NumBytes)*8);
+                                  ByteShift * BitsPerAU,
+                                  (ByteShift + NumBytes) * BitsPerAU);
   if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
 
   // Check that it is legal on the target to do this.  It is legal if the new
   // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
   // legalization.
-  MVT VT = MVT::getIntegerVT(NumBytes*8);
+  MVT VT = MVT::getIntegerVT(NumBytes*BitsPerAU);
   if (!DC->isTypeLegal(VT))
     return nullptr;
 
   // Okay, we can do this!  Replace the 'St' store with a store of IVal that is
   // shifted by ByteShift and truncated down to NumBytes.
   if (ByteShift) {
     SDLoc DL(IVal);
     IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal,
-                       DAG.getConstant(ByteShift*8, DL,
+                       DAG.getConstant(ByteShift * BitsPerAU, DL,
                                     DC->getShiftAmountTy(IVal.getValueType())));
   }
 
   // Figure out the offset for the store and the alignment of the access.
   unsigned StOffset;
   unsigned NewAlign = St->getAlignment();
 
   if (DAG.getDataLayout().isLittleEndian())
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
     if (ShAmt % NewBW)
       ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
     APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
                                    std::min(BitWidth, ShAmt + NewBW));
     if ((Imm & Mask) == Imm) {
       APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
       if (Opc == ISD::AND)
         NewImm ^= APInt::getAllOnesValue(NewBW);
-      uint64_t PtrOff = ShAmt / 8;
+      uint64_t PtrOff = ShAmt / bitsPerAU();
       // For big endian targets, we need to adjust the offset to the pointer to
       // load the correct bytes.
       if (DAG.getDataLayout().isBigEndian())
-        PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
+        PtrOff = inAUs(BitWidth - NewBW) - PtrOff;
 
       unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
       Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
       if (NewAlign < DAG.getDataLayout().getABITypeAlignment(NewVTTy))
         return SDValue();
 
       SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
                                    Ptr.getValueType(), Ptr,
bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
 
   if (MemVT.getSizeInBits() * 2 > MaximumLegalStoreInBits)
     return false;
 
   bool NoVectors = DAG.getMachineFunction().getFunction().hasFnAttribute(
       Attribute::NoImplicitFloat);
 
   // This function cannot currently deal with non-byte-sized memory sizes.
-  if (ElementSizeBytes * 8 != MemVT.getSizeInBits())
+  if (ElementSizeBytes * bitsPerAU() != MemVT.getSizeInBits())
     return false;
 
   if (!MemVT.isSimple())
     return false;
 
   // Perform an early exit check. Do not bother looking at stored values that
   // are not constants, loads, or extracted vector elements.
   SDValue StoredVal = peekThroughBitcasts(St->getValue());
if (IsConstantSrc) {
             IsElementZero = C->getConstantFPValue()->isNullValue();
           if (IsElementZero) {
             if (NonZero && FirstZeroAfterNonZero == NumConsecutiveStores)
               FirstZeroAfterNonZero = i;
           }
           NonZero |= !IsElementZero;
 
           // Find a legal type for the constant store.
-          unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8;
+          unsigned SizeInBits = (i + 1) * ElementSizeBytes * bitsPerAU();
           EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);
           bool IsFast = false;
 
           // Break early when size is too large to be legal.
           if (StoreTy.getSizeInBits() > MaximumLegalStoreInBits)
             break;
 
           if (TLI.isTypeLegal(StoreTy) &&
while (NumConsecutiveStores >= 2 && LoadNodes.size() >= 2) {
             IsFastSt &&
             TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstLoadAS,
                                    FirstLoadAlign, &IsFastLd) &&
             IsFastLd) {
           LastLegalVectorType = i + 1;
         }
 
         // Find a legal type for the integer store.
-        unsigned SizeInBits = (i + 1) * ElementSizeBytes * 8;
+        unsigned SizeInBits = (i + 1) * ElementSizeBytes * bitsPerAU();
         StoreTy = EVT::getIntegerVT(Context, SizeInBits);
         if (TLI.isTypeLegal(StoreTy) &&
             TLI.canMergeStoresTo(FirstStoreAS, StoreTy, DAG) &&
             TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
                                    FirstStoreAlign, &IsFastSt) &&
             IsFastSt &&
             TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstLoadAS,
                                    FirstLoadAlign, &IsFastLd) &&
while (NumConsecutiveStores >= 2 && LoadNodes.size() >= 2) {
       // Find if it is better to use vectors or integers to load and store
       // to memory.
       EVT JointMemOpVT;
       if (UseVectorTy) {
         // Find a legal type for the vector store.
         unsigned Elts = NumElem * NumMemElts;
         JointMemOpVT = EVT::getVectorVT(Context, MemVT.getScalarType(), Elts);
       } else {
-        unsigned SizeInBits = NumElem * ElementSizeBytes * 8;
+        unsigned SizeInBits = NumElem * ElementSizeBytes * bitsPerAU();
         JointMemOpVT = EVT::getIntegerVT(Context, SizeInBits);
       }
 
       SDLoc LoadDL(LoadNodes[0].MemNode);
       SDLoc StoreDL(StoreNodes[0].MemNode);
 
       // The merged loads are required to have the same incoming chain, so
       // using the first's chain is acceptable.
if (!ST->isVolatile() &&
       SDValue Hi = DAG.getConstant(Val >> 32, SDLoc(CFP), MVT::i32);
       if (DAG.getDataLayout().isBigEndian())
         std::swap(Lo, Hi);
 
       unsigned Alignment = ST->getAlignment();
       MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
       AAMDNodes AAInfo = ST->getAAInfo();
 
+      // Calculate the offset in bytes.
+      const unsigned HalfSize = 32 / bitsPerAU();
       SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
                                  ST->getAlignment(), MMOFlags, AAInfo);
       Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
-                        DAG.getConstant(4, DL, Ptr.getValueType()));
-      Alignment = MinAlign(Alignment, 4U);
+                        DAG.getConstant(HalfSize, DL, Ptr.getValueType()));
+      Alignment = MinAlign(Alignment, HalfSize);
       SDValue St1 = DAG.getStore(Chain, DL, Hi, Ptr,
-                                 ST->getPointerInfo().getWithOffset(4),
+                                 ST->getPointerInfo().getWithOffset(HalfSize),
                                  Alignment, MMOFlags, AAInfo);
       return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                          St0, St1);
     }
 
     return SDValue();
   }
 }
case ISD::LIFETIME_END:
       break;
     case ISD::STORE: {
       StoreSDNode *ST = dyn_cast<StoreSDNode>(Chain);
       if (ST->isVolatile() || ST->isIndexed())
         continue;
       const BaseIndexOffset StoreBase = BaseIndexOffset::match(ST, DAG);
       // If we store purely within object bounds just before its lifetime ends,
       // we can remove the store.
-      if (LifetimeEndBase.contains(DAG, LifetimeEnd->getSize() * 8, StoreBase,
+      if (LifetimeEndBase.contains(DAG, LifetimeEnd->getSize() * bitsPerAU(),
+                                   StoreBase,
                                    ST->getMemoryVT().getStoreSizeInBits())) {
         LLVM_DEBUG(dbgs() << "\nRemoving store:"; StoreBase.dump();
                    dbgs() << "\nwithin LIFETIME_END of : ";
                    LifetimeEndBase.dump(); dbgs() << "\n");
         CombineTo(ST, ST->getChain());
         return SDValue(N, 0);
       }
     }
SDValue DAGCombiner::splitMergedValStore(StoreSDNode *ST) {
   Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Lo.getOperand(0));
   Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Hi.getOperand(0));
 
   SDValue Chain = ST->getChain();
   SDValue Ptr = ST->getBasePtr();
   // Lower value store.
   SDValue St0 = DAG.getStore(Chain, DL, Lo, Ptr, ST->getPointerInfo(),
                              ST->getAlignment(), MMOFlags, AAInfo);
+  const unsigned HalfValByteSize = HalfValBitSize / bitsPerAU();
   Ptr =
       DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
-                  DAG.getConstant(HalfValBitSize / 8, DL, Ptr.getValueType()));
+                  DAG.getConstant(HalfValByteSize, DL, Ptr.getValueType()));
   // Higher value store.
   SDValue St1 =
       DAG.getStore(St0, DL, Hi, Ptr,
-                   ST->getPointerInfo().getWithOffset(HalfValBitSize / 8),
+                   ST->getPointerInfo().getWithOffset(HalfValByteSize),
                    Alignment / 2, MMOFlags, AAInfo);
   return St1;
 }
 
 /// Convert a disguised subvector insertion into a shuffle:
 /// insert_vector_elt V, (bitcast X from vector type), IdxC -->
 /// bitcast(shuffle (bitcast V), (extended X), Mask)
 /// Note: We do not use an insert_subvector node because that requires a legal
SDValue DAGCombiner::scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
 
   SDValue NewPtr = OriginalLoad->getBasePtr();
   SDValue Offset;
   EVT PtrType = NewPtr.getValueType();
   MachinePointerInfo MPI;
   SDLoc DL(EVE);
   if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
     int Elt = ConstEltNo->getZExtValue();
-    unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
+    unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / bitsPerAU();
     Offset = DAG.getConstant(PtrOff, DL, PtrType);
     MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
   } else {
     Offset = DAG.getZExtOrTrunc(EltNo, DL, PtrType);
     Offset = DAG.getNode(
         ISD::MUL, DL, PtrType, Offset,
         DAG.getConstant(VecEltVT.getStoreSize(), DL, PtrType));
     // Discard the pointer info except the address space because the memory
auto BuildClearMask = [&](int Split) {
     SDValue Zero = DAG.getConstant(0, DL, ClearVT);
     return DAG.getBitcast(VT, DAG.getVectorShuffle(ClearVT, DL,
                                                    DAG.getBitcast(ClearVT, LHS),
                                                    Zero, Indices));
   };
 
   // Determine maximum split level (byte level masking).
   int MaxSplit = 1;
-  if (RVT.getScalarSizeInBits() % 8 == 0)
-    MaxSplit = RVT.getScalarSizeInBits() / 8;
+  if (RVT.getScalarSizeInBits() % bitsPerAU() == 0)
+    MaxSplit = RVT.getScalarSizeInBits() / bitsPerAU();
 
   for (int Split = 1; Split <= MaxSplit; ++Split)
     if (RVT.getScalarSizeInBits() % Split == 0)
       if (SDValue S = BuildClearMask(Split))
         return S;
 
   return SDValue();
 }
bool DAGCombiner::parallelizeChainedStores(StoreSDNode *St) {
   if (!BasePtr.getBase().getNode())
     return false;
 
   // Do not handle stores to undef base pointers.
   if (BasePtr.getBase().isUndef())
     return false;
 
   // Add ST's interval.
-  Intervals.insert(0, (St->getMemoryVT().getSizeInBits() + 7) / 8, Unit);
+  Intervals.insert(0, inAUs(St->getMemoryVT().getSizeInBits()), Unit);
 
   while (StoreSDNode *Chain = dyn_cast<StoreSDNode>(STChain->getChain())) {
     // If the chain has more than one use, then we can't reorder the mem ops.
     if (!SDValue(Chain, 0)->hasOneUse())
       break;
     if (Chain->isVolatile() || Chain->isIndexed())
       break;
 
     // Find the base pointer and offset for this memory node.
     const BaseIndexOffset Ptr = BaseIndexOffset::match(Chain, DAG);
     // Check that the base pointer is the same as the original one.
     int64_t Offset;
     if (!BasePtr.equalBaseIndex(Ptr, DAG, Offset))
       break;
-    int64_t Length = (Chain->getMemoryVT().getSizeInBits() + 7) / 8;
+    int64_t Length = inAUs(Chain->getMemoryVT().getSizeInBits());
     // Make sure we don't overlap with other intervals by checking the ones to
     // the left or right before inserting.
     auto I = Intervals.find(Offset);
     // If there's a next interval, we should end before it.
     if (I != Intervals.end() && I.start() < (Offset + Length))
       break;
     // If there's a previous interval, we should start after it.
     if (I != Intervals.begin() && (--I).stop() <= Offset)

lib/IR/DataLayout.cpp

void DataLayout::reset(StringRef Desc) {
   clear();
 
   LayoutMap = nullptr;
   BigEndian = false;
   AllocaAddrSpace = 0;
   StackNaturalAlign = 0;
   ProgramAddrSpace = 0;
   FunctionPtrAlign = 0;
+  BitsPerAddressableUnit = 8;
   TheFunctionPtrAlignType = FunctionPtrAlignType::Independent;
   ManglingMode = MM_None;
   NonIntegralAddressSpaces.clear();
 
   // Default alignments
   for (const LayoutAlignElem &E : DefaultAlignments) {
     setAlignment((AlignTypeEnum)E.AlignType, E.ABIAlign, E.PrefAlign,
                  E.TypeBitWidth);