ARMEB: Vector narrow operations

[cpirker]

Summary

Hi all,

This patch implements correct vector narrow operations from <2 x 64> to <2 x 8>, <2 x 16>, and <2 x 32> and from <4 x 32 > to <4 x 8>, <4 x 16> vector type for big endian.
It applies to both integer and float type vectors. The CLANG vectorizer is likely to generate such vector extensions for array type casts.
You may also look into D4043, that covers the vector extension operations.

Please review.

Thanks,
Christian

[cpirker]

Extensive testing showed that this was the wrong approach, as it has broken some tests.
I will issue another patch later this week.

Thanks,
Christian

lib/Target/ARM/ARMISelLowering.cpp

if (OpNum == OP_COPY) {
     assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
     return RHS;
   }
 
   SDValue OpLHS, OpRHS;
   OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
   OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
   EVT VT = OpLHS.getValueType();
+  bool IsBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
 
   switch (OpNum) {
   default: llvm_unreachable("Unknown shuffle opcode!");
   case OP_VREV:
     // VREV divides the vector in half and swaps within the half.
     if (VT.getVectorElementType() == MVT::i32 ||
         VT.getVectorElementType() == MVT::f32)
       return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
   case OP_VEXT2:
   case OP_VEXT3:
     return DAG.getNode(ARMISD::VEXT, dl, VT,
                        OpLHS, OpRHS,
                        DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
   case OP_VUZPL:
   case OP_VUZPR:
     return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
-                       OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
+                       OpLHS, OpRHS).getValue(IsBigEndian ? 1-OpNum+OP_VUZPL :
+                                                            OpNum-OP_VUZPL);
   case OP_VZIPL:
   case OP_VZIPR:
     return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
-                       OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
+                       OpLHS, OpRHS).getValue(IsBigEndian ? 1-OpNum+OP_VZIPL :
+                                                            OpNum-OP_VZIPL);
   case OP_VTRNL:
   case OP_VTRNR:
     return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
-                       OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
+                       OpLHS, OpRHS).getValue(IsBigEndian ? 1-OpNum+OP_VTRNL :
+                                                            OpNum-OP_VTRNL);
   }
 }
 
 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
                                        ArrayRef<int> ShuffleMask,
                                        SelectionDAG &DAG) {
   // Check to see if we can use the VTBL instruction.
   SDValue V1 = Op.getOperand(0);
if (EltSize <= 32) {
     }
 
     // Check for Neon shuffles that modify both input vectors in place.
     // If both results are used, i.e., if there are two shuffles with the same
     // source operands and with masks corresponding to both results of one of
     // these operations, DAG memoization will ensure that a single node is
     // used for both shuffles.
     unsigned WhichResult;
+    unsigned SwapResult = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
     if (isVTRNMask(ShuffleMask, VT, WhichResult))
       return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
-                         V1, V2).getValue(WhichResult);
+                         V1, V2).getValue(WhichResult^SwapResult);
     if (isVUZPMask(ShuffleMask, VT, WhichResult))
       return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
-                         V1, V2).getValue(WhichResult);
+                         V1, V2).getValue(WhichResult^SwapResult);
     if (isVZIPMask(ShuffleMask, VT, WhichResult))
       return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
-                         V1, V2).getValue(WhichResult);
+                         V1, V2).getValue(WhichResult^SwapResult);
 
     if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
       return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
-                         V1, V1).getValue(WhichResult);
+                         V1, V1).getValue(WhichResult^SwapResult);
     if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
       return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
-                         V1, V1).getValue(WhichResult);
+                         V1, V1).getValue(WhichResult^SwapResult);
     if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
       return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
-                         V1, V1).getValue(WhichResult);
+                         V1, V1).getValue(WhichResult^SwapResult);
   }
 
   // If the shuffle is not directly supported and it has 4 elements, use
   // the PerfectShuffle-generated table to synthesize it from other shuffles.
   unsigned NumElts = VT.getVectorNumElements();
   if (NumElts == 4) {
     unsigned PFIndexes[4];
     for (unsigned i = 0; i != 4; ++i) {

test/CodeGen/ARM/big-endian-neon-narrow.ll

+; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
+
+define void @vector_narrow_2i64_to_2i32( <2 x i64>* %loadaddr, <2 x i32>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_2i64_to_2i32:
+; CHECK:       vmovn.i64 [[REG:d[0-9]+]]
+; CHECK:       vrev64.32  [[REG]], [[REG]]
+  %1 = load <2 x i64>* %loadaddr
+  %2 = trunc <2 x i64> %1 to <2 x i32>
+  store <2 x i32> %2, <2 x i32>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_2i64_to_2i16( <2 x i64>* %loadaddr, <2 x i16>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_2i64_to_2i16:
+; CHECK:       vmovn.i64  [[REG:d[0-9]+]]
+; CHECK:       vrev32.16  [[REG]], [[REG]]
+; CHECK:       vuzp.16    [[REG]], [[REG2:d[0-9]+]]
+; CHECK:       vrev32.16  [[REG]], [[REG2]]
+  %1 = load <2 x i64>* %loadaddr
+  %2 = trunc <2 x i64> %1 to <2 x i16>
+  store <2 x i16> %2, <2 x i16>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_2i64_to_2i8( <2 x i64>* %loadaddr, <2 x i8>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_2i64_to_2i8:
+; CHECK:       vmovn.i64 [[REG:d[0-9]+]]
+; CHECK:       vmov.32 r0, [[REG:d[0-9]+]][1]
+; CHECK:       strb  r0, [r1, #1]
+; CHECK:       vmov.32 r0, [[REG:d[0-9]+]][0]
+; CHECK:       strb  r0, [r1]
+  %1 = load <2 x i64>* %loadaddr
+  %2 = trunc <2 x i64> %1 to <2 x i8>
+  store <2 x i8> %2, <2 x i8>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_4i32_to_4i16( <4 x i32>* %loadaddr, <4 x i16>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_4i32_to_4i16:
+; CHECK:       vmovn.i32 [[REG:d[0-9]+]]
+; CHECK:       vrev64.16  [[REG]], [[REG]]
+  %1 = load <4 x i32>* %loadaddr
+  %2 = trunc <4 x i32> %1 to <4 x i16>
+  store <4 x i16> %2, <4 x i16>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_4i32_to_4i8( <4 x i32>* %loadaddr, <4 x i8>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_4i32_to_4i8:
+; CHECK:       vmovn.i32 [[REG:d[0-9]+]]
+; CHECK:       vrev16.8  [[REG]], [[REG]]
+; CHECK:       vuzp.8    [[REG]], [[REG2:d[0-9]+]]
+; CHECK:       vrev32.8  [[REG]], [[REG2]]
+  %1 = load <4 x i32>* %loadaddr
+  %2 = trunc <4 x i32> %1 to <4 x i8>
+  store <4 x i8> %2, <4 x i8>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_8i16_to_8i8( <8 x i16>* %loadaddr, <8 x i8>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_8i16_to_8i8:
+; CHECK:       vmovn.i16 [[REG:d[0-9]+]]
+; CHECK:       vrev64.8  [[REG]], [[REG]]
+  %1 = load <8 x i16>* %loadaddr
+  %2 = trunc <8 x i16> %1 to <8 x i8>
+  store <8 x i8> %2, <8 x i8>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_2i32_to_2i16( <2 x i32>* %loadaddr, <2 x i16>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_2i32_to_2i16:
+; CHECK:       vuzp.16    [[REG:d[0-9]+]], [[REG2:d[0-9]+]]
+; CHECK:       vrev32.16  [[REG]], [[REG2]]
+  %1 = load <2 x i32>* %loadaddr
+  %2 = trunc <2 x i32> %1 to <2 x i16>
+  store <2 x i16> %2, <2 x i16>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_2i32_to_2i8( <2 x i32>* %loadaddr, <2 x i8>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_2i32_to_2i8:
+; CHECK:       vrev64.32 [[REG:d[0-9]+]]
+; CHECK:       vmov.32 r0, [[REG:d[0-9]+]][1]
+; CHECK:       strb  r0, [r1, #1]
+; CHECK:       vmov.32 r0, [[REG]][0]
+; CHECK:       strb  r0, [r1]
+  %1 = load <2 x i32>* %loadaddr
+  %2 = trunc <2 x i32> %1 to <2 x i8>
+  store <2 x i8> %2, <2 x i8>* %storeaddr
+  ret void
+}
+
+define void @vector_narrow_2i16_to_2i8( <2 x i16>* %loadaddr, <2 x i8>* %storeaddr ) {
+; CHECK-LABEL: vector_narrow_2i16_to_2i8:
+; CHECK:       vmov.32 r0, [[REG:d[0-9]+]][1]
+; CHECK:       strb  r0, [r1, #1]
+; CHECK:       vmov.32 r0, [[REG]][0]
+; CHECK:       strb  r0, [r1]
+  %1 = load <2 x i16>* %loadaddr
+  %2 = trunc <2 x i16> %1 to <2 x i8>
+  store <2 x i8> %2, <2 x i8>* %storeaddr
+  ret void
+}
+