[NDS32 43/46] Support parsing/encode/decode for Branch/call Instructions

[shiva0217]

Summary

Support parsing/encode/decode for Branch/call Instructions

lib/Target/NDS32/AsmParser/NDS32AsmParser.cpp

bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
 
   bool ParseDirective(AsmToken DirectiveID) override;
 
   OperandMatchResultTy parseImm(OperandVector &Operands);
 
   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
 
+  OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
+
   bool parseOperand(OperandVector &, StringRef Mnemonic);
 
   int matchCPURegisterName(StringRef Symbol);
   int matchMRegisterName(StringRef Symbol);
   int tryParseRegister();
 
 public:
   enum NDS32MatchResultTy {
int NDS32AsmParser::tryParseRegister() {
   const AsmToken &Tok = Parser.getTok();
   if (Tok.isNot(AsmToken::Identifier)) return -1;
   std::string lowerCase = Tok.getString().lower();
   unsigned RegNum = MatchRegisterName(lowerCase);
   Parser.Lex(); // Eat identifier token.
   return RegNum;
 }
 
+OperandMatchResultTy
+NDS32AsmParser::parseJumpTarget(OperandVector &Operands) {
+  MCAsmParser &Parser = getParser();
+  DEBUG(dbgs() << "parseJumpTarget\n");
+
+  SMLoc S = getLexer().getLoc();
+
+  // Integers and expressions are acceptable
+  OperandMatchResultTy ResTy = parseImm(Operands);
+  if (ResTy != MatchOperand_NoMatch)
+    return ResTy;
+
+  const MCExpr *Expr = nullptr;
+  if (Parser.parseExpression(Expr)) {
+    // We have no way of knowing if a symbol was consumed so we must ParseFail
+    return MatchOperand_ParseFail;
+  }
+  Operands.push_back(
+      NDS32Operand::CreateImm(Expr, S, getLexer().getLoc(), *this));
+  return MatchOperand_Success;
+}
+
 bool NDS32AsmParser::
 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                  SMLoc NameLoc, OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   DEBUG(dbgs() << "ParseInstruction\n");
 
   // Check if we have valid mnemonic
   if (!mnemonicIsValid(Name, 0)) {
default:
     return Match_Success;
   }
 }
 
 bool NDS32AsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
   MCAsmParser &Parser = getParser();
   DEBUG(dbgs() << "parseOperand\n");
 
+  // Check if the current operand has a custom associated parser, if so, try to
+  // custom parse the operand, or fallback to the general approach.
+  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
+  if (ResTy == MatchOperand_Success)
+    return false;
+  // If there wasn't a custom match, try the generic matcher below. Otherwise,
+  // there was a match, but an error occurred, in which case, just return that
+  // the operand parsing failed.
+  if (ResTy == MatchOperand_ParseFail)
+    return true;
+
   switch (getLexer().getKind()) {
   default:
     Error(Parser.getTok().getLoc(), "unexpected token in operand");
     return true;
   case AsmToken::Dollar: {
     // Parse the register.
     if (parseAnyRegister(Operands) != MatchOperand_NoMatch)
       return false;

lib/Target/NDS32/Disassembler/NDS32Disassembler.cpp

if (RegNo > 7)
     return MCDisassembler::Fail;
   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
                                      unsigned Offset,
                                      uint64_t Address,
                                      const void *Decoder) {
+  int32_t BranchOffset = (SignExtend32<24>(Offset) * 2);
+  Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
                                        unsigned Offset,
                                        uint64_t Address,
                                        const void *Decoder) {
+  int32_t BranchOffset = (SignExtend32<14>(Offset) * 2);
+  Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeBranchZeroTarget(MCInst &Inst,
                                            unsigned Offset,
                                            uint64_t Address,
                                            const void *Decoder) {
+  int32_t BranchOffset = (SignExtend32<16>(Offset) * 2);
+  Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeBranchTargetImm8s(MCInst &Inst,
                                             unsigned Offset,
                                             uint64_t Address,
                                             const void *Decoder) {
+  int32_t BranchOffset = (SignExtend32<8>(Offset) * 2);
+  Inst.addOperand(MCOperand::createImm(BranchOffset));
   return MCDisassembler::Success;
 }
 
 // Decode [Reg + Imm] addressing mode
 static DecodeStatus DecodeAddrRegImm(MCInst &Inst,
                                      unsigned Insn,
                                      uint64_t Address,
                                      const void *Decoder,

lib/Target/NDS32/MCTargetDesc/NDS32AsmBackend.cpp

 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 // Prepare value for the target space for it
 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
                                  MCContext *Ctx = nullptr) {
+  unsigned Kind = Fixup.getKind();
+
+  switch (Kind) {
+  default:
+    return 0;
+  case FK_Data_1:
+  case FK_Data_2:
+  case FK_Data_4:
+  case FK_SecRel_2:
+  case FK_SecRel_4:
+    break;
+  case NDS32::fixup_NDS32_9_32BIT_INSN_PCREL_RELA:
+  case NDS32::fixup_NDS32_9_PCREL_RELA:
+    if (!isInt<9>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC9 fixup");
       return 0;
     }
+    Value >>= 1;
+    break;
+  case NDS32::fixup_NDS32_15_PCREL_RELA:
+    if (!isInt<15>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC15 fixup");
+      return 0;
+    }
+    Value >>= 1;
+    break;
+  case NDS32::fixup_NDS32_17_PCREL_RELA:
+    if (!isInt<17>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC17 fixup");
+      return 0;
+    }
+    Value >>= 1;
+    break;
+  case NDS32::fixup_NDS32_25_PCREL_RELA:
+    if (!isInt<25>(Value) && Ctx) {
+      Ctx->reportError(Fixup.getLoc(), "out of range PC25 fixup");
+      return 0;
+    }
+    Value >>= 1;
+    break;
+  }
+  return Value;
+}
 
 MCObjectWriter *
 NDS32AsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
   return createNDS32ELFObjectWriter(OS,
     MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, false);
 }
 
 /// getFixupKindContainerSizeBytes - The number of bytes of the

lib/Target/NDS32/MCTargetDesc/NDS32MCCodeEmitter.cpp

 
 /// getBranchTargetImm8sEncoding - Return binary encoding of the branch
 /// target operand. If the machine operand requires relocation,
 /// record the relocation and return zero.
 unsigned NDS32MCCodeEmitter::
 getBranchTargetImm8sEncoding(const MCInst &MI, unsigned OpNo,
                              SmallVectorImpl<MCFixup> &Fixups,
                              const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  // If the destination is an immediate, divide by 2.
+  if (MO.isImm()) return MO.getImm() >> 1;
+
+  assert(MO.isExpr() &&
+         "getBranchTargetImm8sEncoding expects only expressions or immediates");
+
+  const MCExpr *Expr = MO.getExpr();
+  MCFixupKind Kind = MCFixupKind(NDS32::fixup_NDS32_9_PCREL_RELA);
+  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
   return 0;
 }
 
 // Just like getBranchTargetImm8sEncoding but for 32 bit instruction
 unsigned NDS32MCCodeEmitter::
 getBranchTargetImm8s32BitEncoding(const MCInst &MI, unsigned OpNo,
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  // If the destination is an immediate, divide by 2.
+  if (MO.isImm()) return MO.getImm() >> 1;
+
+  assert(MO.isExpr() &&
+         "getBranchTargetImm8sEncoding expects only expressions or immediates");
+
+  const MCExpr *Expr = MO.getExpr();
+  MCFixupKind Kind = MCFixupKind(NDS32::fixup_NDS32_9_32BIT_INSN_PCREL_RELA);
+  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
   return 0;
 }
 
 /// getBranchTargetOpValue - Return encoding info for 14-bit branch target.
 unsigned NDS32MCCodeEmitter::
 getBranchTargetEncoding(const MCInst &MI, unsigned OpNo,
                         SmallVectorImpl<MCFixup> &Fixups,
                         const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  if (MO.isImm()) return MO.getImm();
+
+  const MCExpr *Expr = MO.getExpr();
+  MCFixupKind Kind = MCFixupKind(NDS32::fixup_NDS32_15_PCREL_RELA);
+  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+
   return 0;
 }
 
 /// getBranchZeroTargetOpValue - Return encoding info for 16-bit branch target.
 unsigned NDS32MCCodeEmitter::
 getBranchZeroTargetEncoding(const MCInst &MI, unsigned OpNo,
                             SmallVectorImpl<MCFixup> &Fixups,
                             const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  if (MO.isImm()) return MO.getImm();
+
+  const MCExpr *Expr = MO.getExpr();
+  MCFixupKind Kind = MCFixupKind(NDS32::fixup_NDS32_17_PCREL_RELA);
+  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+
   return 0;
 }
 
 /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch
 /// target.
 uint32_t NDS32MCCodeEmitter::
 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
                      SmallVectorImpl<MCFixup> &Fixups,
                      const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+
+  // If the destination is an immediate, we have nothing to do.
+  if (MO.isImm()) return MO.getImm();
+  assert(MO.isExpr() && "Unexpected branch target type!");
+  const MCExpr *Expr = MO.getExpr();
+  MCFixupKind Kind = MCFixupKind(NDS32::fixup_NDS32_25_PCREL_RELA);
+  Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
+
   return 0;
 }
 
 /// getRegisterListEncoding - Return encoding for mutiple
 /// load/store Register list
 uint32_t NDS32MCCodeEmitter::
 getRegisterListEncoding(const MCInst &MI, unsigned OpNo,
                         SmallVectorImpl<MCFixup> &Fixups,
                         const MCSubtargetInfo &STI) const {
   return 0;
 }
 
 #include "NDS32GenMCCodeEmitter.inc"

lib/Target/NDS32/NDS32Predicate.td

def reglist : Operand<i32> {
   let ParserMatchClass = RegListAsmOperand;
 }
 
 
 //===----------------------------------------------------------------------===//
 // Branch/Jump target Operands Predicates
 //
 
+def NDS32JumpTarget : AsmOperandClass {
+  let Name = "NDS32JumpTarget";
+  let ParserMethod = "parseJumpTarget";
+  let PredicateMethod = "isImm";
+  let RenderMethod = "addImmOperands";
+}
+
 def nds32_jump_target : Operand<OtherVT> {
+  let ParserMatchClass = NDS32JumpTarget;
   let OperandType = "OPERAND_PCREL";
 }
 
 def nds32_jal_target : Operand<i32> {
+  let ParserMatchClass = NDS32JumpTarget;
+  let EncoderMethod = "getJumpTargetOpValue";
+  let DecoderMethod = "DecodeJumpTarget";
   let OperandType = "OPERAND_PCREL";
 }
 
 def nds32_j_target : Operand<OtherVT> {
+  let ParserMatchClass = NDS32JumpTarget;
+  let EncoderMethod = "getJumpTargetOpValue";
+  let DecoderMethod = "DecodeJumpTarget";
   let OperandType = "OPERAND_PCREL";
 }
 
 def brtarget : Operand<OtherVT> {
+  let ParserMatchClass = NDS32JumpTarget;
+  let EncoderMethod = "getBranchTargetEncoding";
+  let DecoderMethod = "DecodeBranchTarget";
   let OperandType = "OPERAND_PCREL";
 }
 
 def brzerotarget : Operand<OtherVT> {
+  let ParserMatchClass = NDS32JumpTarget;
+  let EncoderMethod = "getBranchZeroTargetEncoding";
+  let DecoderMethod = "DecodeBranchZeroTarget";
   let OperandType = "OPERAND_PCREL";
 }
 
 def brtargetImm8s : Operand<OtherVT> {
+  let ParserMatchClass = NDS32JumpTarget;
+  let EncoderMethod = "getBranchTargetImm8sEncoding";
+  let DecoderMethod = "DecodeBranchTargetImm8s";
   let OperandType = "OPERAND_PCREL";
 }
 
 def brtargetImm8s_32bit : Operand<OtherVT> {
+  let ParserMatchClass = NDS32JumpTarget;
+  let EncoderMethod = "getBranchTargetImm8s32BitEncoding";
+  let DecoderMethod = "DecodeBranchTargetImm8s";
   let OperandType = "OPERAND_PCREL";
 }
 
 
 //===----------------------------------------------------------------------===//
 // 16 Bit Load/Store Instruction Operands Predicates
 //
 

test/MC/NDS32/nds32-branches.s

+! RUN: llvm-mc -triple nds32 -filetype=obj -o %t %s
+! RUN:    llvm-objdump -d -r -triple nds32 %t | FileCheck %s
+foo:
+        j .LBB0_1
+        jal .LBB0_1
+  beq     $r1, $r0, .LBB0_1
+  bne     $r1, $r0, .LBB0_1
+  bnez    $r2, .LBB0_1
+  beqz    $r2, .LBB0_1
+  bgtz    $r2, .LBB0_1
+  bgez    $r2, .LBB0_1
+  bltz    $r2, .LBB0_1
+  blez    $r2, .LBB0_1
+  beqc    $r1, 2, .LBB0_1
+  bnec    $r1, 2, .LBB0_1
+  beqz38  $r2, .LBB0_1
+  bnez38  $r2, .LBB0_1
+.LBB0_1:
+
+! CHECK: 48 00 00 1a  j 52
+! CHECK: 49 00 00 18  jal 48
+! CHECK: 4c 10 00 16   beq  $r1, $r0, 44
+! CHECK: 4c 10 40 14   bne  $r1, $r0, 40
+! CHECK: 4e 23 00 12   bnez  $r2, 36
+! CHECK: 4e 22 00 10   beqz  $r2, 32
+! CHECK: 4e 26 00 0e   bgtz  $r2, 28
+! CHECK: 4e 24 00 0c   bgez  $r2, 24
+! CHECK: 4e 25 00 0a   bltz  $r2, 20
+! CHECK: 4e 27 00 08   blez  $r2, 16
+! CHECK: 5a 10 02 06   beqc  $r1, 2, 12
+! CHECK: 5a 18 02 04   bnec  $r1, 2, 8
+! CHECK: c2 02  beqz38  $r2, 4
+! CHECK: ca 01  bnez38  $r2, 2

test/MC/NDS32/reloc-call.s

+! RUN: llvm-mc -triple=nds32 -filetype=obj %s -o - | \
+! RUN:   llvm-readobj -r | FileCheck -check-prefix=OBJ %s
+  .globl  bar
+  .type bar,@function
+bar:
+  jal foo
+! OBJ:      Relocations [
+! OBJ:        Section {{.*}} .rela.text {
+! OBJ-NEXT:     0x{{[0-9,A-F]+}} R_NDS32_25_PCREL_RELA foo 0x0
+! OBJ:        }
+! OBJ:      ]
+