[NDS32 30/46] Add Sign Extension Instructions

[shiva0217]

Summary

Add Sign Extension Instructions

lib/Target/NDS32/NDS32ISelLowering.cpp

NDS32TargetLowering::NDS32TargetLowering(const TargetMachine &TM,
 
   // Load extented operations for i1 types must be promoted
   for (MVT VT : MVT::integer_valuetypes()) {
     setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1,  Promote);
     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1,  Promote);
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1,  Promote);
   }
 
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
+
   // Post increment load/store are legal in NDS32 ISA
   setIndexedLoadAction(ISD::POST_INC, MVT::i32,  Legal);
   setIndexedLoadAction(ISD::POST_INC, MVT::i16,  Legal);
   setIndexedLoadAction(ISD::POST_INC, MVT::i8,   Legal);
   setIndexedStoreAction(ISD::POST_INC, MVT::i32,  Legal);
   setIndexedStoreAction(ISD::POST_INC, MVT::i16,  Legal);
   setIndexedStoreAction(ISD::POST_INC, MVT::i8,   Legal);
 

lib/Target/NDS32/NDS32Instr16Bit.td

 def OR33      : ALU33< "or33" ,  or, 0b111>;
 def XOR33     : ALU33< "xor33", xor, 0b101>;
 
 def NOT33 : MISC33Form<(outs lGPR:$Rt), (ins lGPR:$Ra),
                        "not33\t$Rt, $Ra",
                        [(set lGPR:$Rt, (not lGPR:$Ra))], 0b011>,
                        Requires<[Has16Bit]>;
 
+class  BFMI333_sextend <string opstr, SDPatternOperator Op,
+                        ValueType vt, bits<3> subop_encode> :
+  BFMI333Form<(outs lGPR:$Rt), (ins lGPR:$Ra),
+              !strconcat(opstr, "\t$Rt, $Ra"),
+              [(set lGPR:$Rt, (Op lGPR:$Ra, vt))],
+              subop_encode>,
+              Requires<[Has16Bit]>;
+
+def SEB33     : BFMI333_sextend< "seb33",    sext_inreg,  i8, 0b010>;
+def SEH33     : BFMI333_sextend< "seh33",    sext_inreg, i16, 0b011>;
+
 
 //===----------------------------------------------------------------------===//
 // Load/Store Instructions
 //
 
 let AddedComplexity = 4, mayLoad = 1 in {
 def LBI333: LBI333Form<(outs lGPR:$Rt), (ins addr_imm3u_byte:$addr),
                        "lbi333\t$Rt, $addr",

lib/Target/NDS32/NDS32Instr16Formats.td

class MISC33Form<dag outs, dag ins, string asmstr, list<dag> pattern,
   : 16BitInst6BitOpcode<0b111111, outs, ins, asmstr, pattern> {
   bits<3> Rt;
   bits<3> Ra;
   let Inst{8-6} = Rt;
   let Inst{5-3} = Ra;
   let Inst{2-0} = subop_encode;
 }
 
+class BFMI333Form<dag outs, dag ins, string asmstr, list<dag> pattern,
+      bits<3> subop_encode>
+  : 16BitInst6BitOpcode<0b001011, outs, ins, asmstr, pattern> {
+  bits<3> Rt;
+  bits<3> Ra;
+  let Inst{8-6} = Rt;
+  let Inst{5-3} = Ra;
+  let Inst{2-0} = subop_encode;
+}
+
 class LBI333Form<dag outs, dag ins, string asmstr, list<dag> pattern>
   : 16BitInst6BitOpcode<0b010011, outs, ins, asmstr, pattern> {
   bits<3> Rt;
   bits<6> addr;
   let Inst{8-6} = Rt;
   let Inst{5-3} = addr{5-3};  // Ra
   let Inst{2-0} = addr{2-0};  // imm3u
 }

lib/Target/NDS32/NDS32InstrInfo.td

 def AND_SRLI     : ALU_shift<"and_srli", and, srl, 0b11110>;
 def OR_SLLI      : ALU_shift<"or_slli" , or,  shl, 0b00100>;
 def OR_SRLI      : ALU_shift<"or_srli" , or,  srl, 0b10101>;
 def XOR_SLLI     : ALU_shift<"xor_slli", xor, shl, 0b00011>;
 def XOR_SRLI     : ALU_shift<"xor_srli", xor, srl, 0b11111>;
 
 
 //===----------------------------------------------------------------------===//
+// Sign Extension Instructions
+//
+
+class ALU_1_sextend <string opstr, SDPatternOperator Op,
+                     ValueType vt, bits<5> subop_encode> :
+  ALU_1Form<(outs GPR:$Rt), (ins GPR:$Ra),
+            !strconcat(opstr, "\t$Rt, $Ra"),
+            [(set GPR:$Rt, (Op GPR:$Ra, vt))]> {
+  bits<5> Rt;
+  bits<5> Ra;
+  let Inst{24-20} = Rt;
+  let Inst{19-15} = Ra;
+  let Inst{14-5} = 0;
+  let Inst{4-0} = subop_encode;
+}
+
+def SEB     : ALU_1_sextend< "seb",    sext_inreg,  i8, 0b10000>;
+def SEH     : ALU_1_sextend< "seh",    sext_inreg, i16, 0b10001>;
+
+
+//===----------------------------------------------------------------------===//
 // Division Instructions
 //
 // In NDS32 ISA, quotient and remainder register set to same register
 // will only set quotient value to the register which match the semantic
 // udiv/sdiv in dags.
 class DIVrr<string opstr, SDPatternOperator Op, bits<5> subop_encode> :
   ALU_1Form<(outs GPR:$Rt), (ins GPR:$Ra, GPR:$Rb),
             !strconcat(opstr, "\t$Rt, $Rt, $Ra, $Rb"),

test/CodeGen/NDS32/sign-extend.ll

+; RUN: llc -mattr=+no-16bit < %s | FileCheck %s
+; RUN: llc < %s | FileCheck --check-prefix=CHECK-16BIT %s
+target datalayout = "e-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "nds32le---elf"
+
+@sign_extend.lastn = internal unnamed_addr global i32 0, align 4
+
+; Function Attrs: norecurse nounwind
+define i32 @sign_extend(i32 %n, i32 %c) local_unnamed_addr #0 {
+entry:
+  %shl = shl i32 %n, 3
+  %xor = xor i32 %shl, -1
+  %sext = shl i32 %xor, 24
+; CHECK: seb     $r3, $r2
+; CHECK-16BIT: seb33     $r3, $r2
+  %conv1 = ashr exact i32 %sext, 24
+  %cmp = icmp eq i32 %conv1, %c
+  br i1 %cmp, label %if.end, label %return
+
+if.end:                                           ; preds = %entry
+  %sext13 = shl i32 %xor, 16
+  %conv6 = ashr exact i32 %sext13, 16
+; CHECK: seh     $r2, $r2
+; CHECK-16BIT: seh33     $r2, $r2
+  %cmp7 = icmp eq i32 %conv6, %c
+  br i1 %cmp7, label %if.end10, label %return
+
+if.end10:                                         ; preds = %if.end
+  %0 = load i32, i32* @sign_extend.lastn, align 4
+  %inc = add nsw i32 %0, 1
+  store i32 %inc, i32* @sign_extend.lastn, align 4
+  br label %return
+
+return:                                           ; preds = %if.end, %entry, %if.end10
+  %retval.0 = phi i32 [ undef, %if.end10 ], [ 1, %entry ], [ 2, %if.end ]
+  ret i32 %retval.0
+}