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Differential D29237

[X86] Fixing flag usage for RCL and RCR
ClosedPublic

Authored by cray on Jan 27 2017, 5:05 PM.

Details

Reviewers
craig.topper
Commits
rGba3741cb2b4d: [X86] Fixing flag usage for RCL and RCR
rL293441: [X86] Fixing flag usage for RCL and RCR
Summary

The RCL and RCR instructions use the carry flag.

Diff Detail

Repository
rL LLVM

Event Timeline

cray created this revision.Jan 27 2017, 5:05 PM
craig.topper accepted this revision.Jan 28 2017, 4:16 PM

LGTM

This revision is now accepted and ready to land.Jan 28 2017, 4:16 PM
Closed by commit rL293441: [X86] Fixing flag usage for RCL and RCR (authored by cray). · Explain WhyJan 29 2017, 12:16 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
1937 lines

Diff 86221

llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td

//===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===// //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file describes the shift and rotate instructions. // This file describes the shift and rotate instructions.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// FIXME: Someone needs to smear multipattern goodness all over this file. // FIXME: Someone needs to smear multipattern goodness all over this file.
let Defs = [EFLAGS] in { let Defs = [EFLAGS] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
"shl{b}\t{%cl, $dst|$dst, cl}", "shl{b}\t{%cl, $dst|$dst, cl}",
[(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>; [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
"shl{w}\t{%cl, $dst|$dst, cl}", "shl{w}\t{%cl, $dst|$dst, cl}",
[(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16; [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
"shl{l}\t{%cl, $dst|$dst, cl}", "shl{l}\t{%cl, $dst|$dst, cl}",
[(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32; [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
"shl{q}\t{%cl, $dst|$dst, cl}", "shl{q}\t{%cl, $dst|$dst, cl}",
[(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>; [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
} // Uses = [CL] } // Uses = [CL]
def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
"shl{b}\t{$src2, $dst|$dst, $src2}", "shl{b}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
"shl{w}\t{$src2, $dst|$dst, $src2}", "shl{w}\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>, [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
OpSize16; OpSize16;
def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
"shl{l}\t{$src2, $dst|$dst, $src2}", "shl{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>, [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
OpSize32; OpSize32;
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
(ins GR64:$src1, u8imm:$src2), (ins GR64:$src1, u8imm:$src2),
"shl{q}\t{$src2, $dst|$dst, $src2}", "shl{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))], [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
IIC_SR>; IIC_SR>;
} // isConvertibleToThreeAddress = 1 } // isConvertibleToThreeAddress = 1
// NOTE: We don't include patterns for shifts of a register by one, because // NOTE: We don't include patterns for shifts of a register by one, because
// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one). // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
"shl{b}\t$dst", [], IIC_SR>; "shl{b}\t$dst", [], IIC_SR>;
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
"shl{w}\t$dst", [], IIC_SR>, OpSize16; "shl{w}\t$dst", [], IIC_SR>, OpSize16;
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
"shl{l}\t$dst", [], IIC_SR>, OpSize32; "shl{l}\t$dst", [], IIC_SR>, OpSize32;
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
"shl{q}\t$dst", [], IIC_SR>; "shl{q}\t$dst", [], IIC_SR>;
} // hasSideEffects = 0 } // hasSideEffects = 0
} // Constraints = "$src = $dst", SchedRW } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in { let SchedRW = [WriteShiftLd, WriteRMW] in {
// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
// using CL? // using CL?
let Uses = [CL] in { let Uses = [CL] in {
def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
"shl{b}\t{%cl, $dst|$dst, cl}", "shl{b}\t{%cl, $dst|$dst, cl}",
[(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>; [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
"shl{w}\t{%cl, $dst|$dst, cl}", "shl{w}\t{%cl, $dst|$dst, cl}",
[(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>, [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
OpSize16; OpSize16;
def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
"shl{l}\t{%cl, $dst|$dst, cl}", "shl{l}\t{%cl, $dst|$dst, cl}",
[(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>, [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
OpSize32; OpSize32;
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
"shl{q}\t{%cl, $dst|$dst, cl}", "shl{q}\t{%cl, $dst|$dst, cl}",
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>; [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
} }
def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src), def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, u8imm:$src),
"shl{b}\t{$src, $dst|$dst, $src}", "shl{b}\t{$src, $dst|$dst, $src}",
[(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>; IIC_SR>;
def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src), def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, u8imm:$src),
"shl{w}\t{$src, $dst|$dst, $src}", "shl{w}\t{$src, $dst|$dst, $src}",
[(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src), def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, u8imm:$src),
"shl{l}\t{$src, $dst|$dst, $src}", "shl{l}\t{$src, $dst|$dst, $src}",
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src), def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, u8imm:$src),
"shl{q}\t{$src, $dst|$dst, $src}", "shl{q}\t{$src, $dst|$dst, $src}",
[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>; IIC_SR>;
// Shift by 1 // Shift by 1
def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
"shl{b}\t$dst", "shl{b}\t$dst",
[(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)], [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
"shl{w}\t$dst", "shl{w}\t$dst",
[(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)], [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
"shl{l}\t$dst", "shl{l}\t$dst",
[(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)], [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
"shl{q}\t$dst", "shl{q}\t$dst",
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW } // SchedRW
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
"shr{b}\t{%cl, $dst|$dst, cl}", "shr{b}\t{%cl, $dst|$dst, cl}",
[(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>; [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
"shr{w}\t{%cl, $dst|$dst, cl}", "shr{w}\t{%cl, $dst|$dst, cl}",
[(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16; [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
"shr{l}\t{%cl, $dst|$dst, cl}", "shr{l}\t{%cl, $dst|$dst, cl}",
[(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32; [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
"shr{q}\t{%cl, $dst|$dst, cl}", "shr{q}\t{%cl, $dst|$dst, cl}",
[(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>; [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
} }
def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2), def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
"shr{b}\t{$src2, $dst|$dst, $src2}", "shr{b}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
"shr{w}\t{$src2, $dst|$dst, $src2}", "shr{w}\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))], [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
"shr{l}\t{$src2, $dst|$dst, $src2}", "shr{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))], [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2), def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
"shr{q}\t{$src2, $dst|$dst, $src2}", "shr{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>; [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
// Shift right by 1 // Shift right by 1
def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
"shr{b}\t$dst", "shr{b}\t$dst",
[(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>; [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
"shr{w}\t$dst", "shr{w}\t$dst",
[(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16; [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
"shr{l}\t$dst", "shr{l}\t$dst",
[(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32; [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
"shr{q}\t$dst", "shr{q}\t$dst",
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>; [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
} // Constraints = "$src = $dst", SchedRW } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in { let SchedRW = [WriteShiftLd, WriteRMW] in {
let Uses = [CL] in { let Uses = [CL] in {
def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
"shr{b}\t{%cl, $dst|$dst, cl}", "shr{b}\t{%cl, $dst|$dst, cl}",
[(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>; [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
"shr{w}\t{%cl, $dst|$dst, cl}", "shr{w}\t{%cl, $dst|$dst, cl}",
[(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>, [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
OpSize16; OpSize16;
def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
"shr{l}\t{%cl, $dst|$dst, cl}", "shr{l}\t{%cl, $dst|$dst, cl}",
[(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>, [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
OpSize32; OpSize32;
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
"shr{q}\t{%cl, $dst|$dst, cl}", "shr{q}\t{%cl, $dst|$dst, cl}",
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>; [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
} }
def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src), def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src),
"shr{b}\t{$src, $dst|$dst, $src}", "shr{b}\t{$src, $dst|$dst, $src}",
[(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>; IIC_SR>;
def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src), def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src),
"shr{w}\t{$src, $dst|$dst, $src}", "shr{w}\t{$src, $dst|$dst, $src}",
[(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src), def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src),
"shr{l}\t{$src, $dst|$dst, $src}", "shr{l}\t{$src, $dst|$dst, $src}",
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src), def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src),
"shr{q}\t{$src, $dst|$dst, $src}", "shr{q}\t{$src, $dst|$dst, $src}",
[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>; IIC_SR>;
// Shift by 1 // Shift by 1
def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
"shr{b}\t$dst", "shr{b}\t$dst",
[(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)], [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
"shr{w}\t$dst", "shr{w}\t$dst",
[(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)], [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
"shr{l}\t$dst", "shr{l}\t$dst",
[(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)], [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
"shr{q}\t$dst", "shr{q}\t$dst",
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW } // SchedRW
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
let Uses = [CL] in { let Uses = [CL] in {
def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
"sar{b}\t{%cl, $dst|$dst, cl}", "sar{b}\t{%cl, $dst|$dst, cl}",
[(set GR8:$dst, (sra GR8:$src1, CL))], [(set GR8:$dst, (sra GR8:$src1, CL))],
IIC_SR>; IIC_SR>;
def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
"sar{w}\t{%cl, $dst|$dst, cl}", "sar{w}\t{%cl, $dst|$dst, cl}",
[(set GR16:$dst, (sra GR16:$src1, CL))], [(set GR16:$dst, (sra GR16:$src1, CL))],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
"sar{l}\t{%cl, $dst|$dst, cl}", "sar{l}\t{%cl, $dst|$dst, cl}",
[(set GR32:$dst, (sra GR32:$src1, CL))], [(set GR32:$dst, (sra GR32:$src1, CL))],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
"sar{q}\t{%cl, $dst|$dst, cl}", "sar{q}\t{%cl, $dst|$dst, cl}",
[(set GR64:$dst, (sra GR64:$src1, CL))], [(set GR64:$dst, (sra GR64:$src1, CL))],
IIC_SR>; IIC_SR>;
} }
def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
"sar{b}\t{$src2, $dst|$dst, $src2}", "sar{b}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))], [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
IIC_SR>; IIC_SR>;
def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
"sar{w}\t{$src2, $dst|$dst, $src2}", "sar{w}\t{$src2, $dst|$dst, $src2}",
[(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))], [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
"sar{l}\t{$src2, $dst|$dst, $src2}", "sar{l}\t{$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))], [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
(ins GR64:$src1, u8imm:$src2), (ins GR64:$src1, u8imm:$src2),
"sar{q}\t{$src2, $dst|$dst, $src2}", "sar{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))], [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
IIC_SR>; IIC_SR>;
// Shift by 1 // Shift by 1
def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
"sar{b}\t$dst", "sar{b}\t$dst",
[(set GR8:$dst, (sra GR8:$src1, (i8 1)))], [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
IIC_SR>; IIC_SR>;
def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
"sar{w}\t$dst", "sar{w}\t$dst",
[(set GR16:$dst, (sra GR16:$src1, (i8 1)))], [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
"sar{l}\t$dst", "sar{l}\t$dst",
[(set GR32:$dst, (sra GR32:$src1, (i8 1)))], [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
"sar{q}\t$dst", "sar{q}\t$dst",
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))], [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
IIC_SR>; IIC_SR>;
} // Constraints = "$src = $dst", SchedRW } // Constraints = "$src = $dst", SchedRW
let SchedRW = [WriteShiftLd, WriteRMW] in { let SchedRW = [WriteShiftLd, WriteRMW] in {
let Uses = [CL] in { let Uses = [CL] in {
def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
"sar{b}\t{%cl, $dst|$dst, cl}", "sar{b}\t{%cl, $dst|$dst, cl}",
[(store (sra (loadi8 addr:$dst), CL), addr:$dst)], [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
IIC_SR>; IIC_SR>;
def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
"sar{w}\t{%cl, $dst|$dst, cl}", "sar{w}\t{%cl, $dst|$dst, cl}",
[(store (sra (loadi16 addr:$dst), CL), addr:$dst)], [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
"sar{l}\t{%cl, $dst|$dst, cl}", "sar{l}\t{%cl, $dst|$dst, cl}",
[(store (sra (loadi32 addr:$dst), CL), addr:$dst)], [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
"sar{q}\t{%cl, $dst|$dst, cl}", "sar{q}\t{%cl, $dst|$dst, cl}",
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)], [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
IIC_SR>; IIC_SR>;
} }
def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src), def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src),
"sar{b}\t{$src, $dst|$dst, $src}", "sar{b}\t{$src, $dst|$dst, $src}",
[(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>; IIC_SR>;
def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src), def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src),
"sar{w}\t{$src, $dst|$dst, $src}", "sar{w}\t{$src, $dst|$dst, $src}",
[(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src), def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src),
"sar{l}\t{$src, $dst|$dst, $src}", "sar{l}\t{$src, $dst|$dst, $src}",
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src), def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src),
"sar{q}\t{$src, $dst|$dst, $src}", "sar{q}\t{$src, $dst|$dst, $src}",
[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
IIC_SR>; IIC_SR>;
// Shift by 1 // Shift by 1
def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
"sar{b}\t$dst", "sar{b}\t$dst",
[(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)], [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
"sar{w}\t$dst", "sar{w}\t$dst",
[(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)], [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>, OpSize16; IIC_SR>, OpSize16;
def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
"sar{l}\t$dst", "sar{l}\t$dst",
[(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)], [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>, OpSize32; IIC_SR>, OpSize32;
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
"sar{q}\t$dst", "sar{q}\t$dst",
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)], [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; IIC_SR>;
} // SchedRW } // SchedRW
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Rotate instructions // Rotate instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
"rcl{b}\t$dst", [], IIC_SR>; let Uses = [CL, EFLAGS] in {
def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
"rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
let Uses = [CL] in def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
"rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
"rcl{w}\t$dst", [], IIC_SR>, OpSize16; "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), } // Uses = [CL, EFLAGS]
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
let Uses = [CL] in let Uses = [EFLAGS] in {
def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16; "rcl{b}\t$dst", [], IIC_SR>;
def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
"rcl{l}\t$dst", [], IIC_SR>, OpSize32; def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32; def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
let Uses = [CL] in "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32; "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
"rcl{q}\t$dst", [], IIC_SR>; "rcl{q}\t$dst", [], IIC_SR>;
def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt), def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
let Uses = [CL] in } // Uses = [EFLAGS]
def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
"rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; let Uses = [CL, EFLAGS] in {
def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
"rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
"rcr{b}\t$dst", [], IIC_SR>; "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt), def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
"rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
let Uses = [CL] in def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
"rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; } // Uses = [CL, EFLAGS]
def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), let Uses = [EFLAGS] in {
"rcr{w}\t$dst", [], IIC_SR>, OpSize16; def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt), "rcr{b}\t$dst", [], IIC_SR>;
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16; def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
let Uses = [CL] in "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16; "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
"rcr{l}\t$dst", [], IIC_SR>, OpSize32; def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt), "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32; def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
let Uses = [CL] in "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32; "rcr{q}\t$dst", [], IIC_SR>;
def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
"rcr{q}\t$dst", [], IIC_SR>; } // Uses = [EFLAGS]
def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; } // Constraints = "$src = $dst"
let Uses = [CL] in
def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1), let SchedRW = [WriteShiftLd, WriteRMW] in {
"rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; let Uses = [EFLAGS] in {
def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
} // Constraints = "$src = $dst" "rcl{b}\t$dst", [], IIC_SR>;
def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt),
let SchedRW = [WriteShiftLd, WriteRMW] in { "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
"rcl{b}\t$dst", [], IIC_SR>; "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, u8imm:$cnt), def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt),
"rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
"rcl{w}\t$dst", [], IIC_SR>, OpSize16; "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, u8imm:$cnt), def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt),
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16; "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
"rcl{l}\t$dst", [], IIC_SR>, OpSize32; "rcl{q}\t$dst", [], IIC_SR>;
def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, u8imm:$cnt), def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt),
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32; "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
"rcl{q}\t$dst", [], IIC_SR>; def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, u8imm:$cnt), "rcr{b}\t$dst", [], IIC_SR>;
"rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt),
"rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
"rcr{b}\t$dst", [], IIC_SR>; "rcr{w}\t$dst", [], IIC_SR>, OpSize16;
def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, u8imm:$cnt), def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt),
"rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
"rcr{w}\t$dst", [], IIC_SR>, OpSize16; "rcr{l}\t$dst", [], IIC_SR>, OpSize32;
def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, u8imm:$cnt), def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt),
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16; "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
"rcr{l}\t$dst", [], IIC_SR>, OpSize32; "rcr{q}\t$dst", [], IIC_SR>;
def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, u8imm:$cnt), def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt),
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32; "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), } // Uses = [EFLAGS]
"rcr{q}\t$dst", [], IIC_SR>;
def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, u8imm:$cnt), let Uses = [CL, EFLAGS] in {
"rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>; def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
"rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
let Uses = [CL] in { def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
"rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16; def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst), def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
"rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
"rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16; def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32; } // Uses = [CL, EFLAGS]
def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), } // SchedRW
"rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>; } // hasSideEffects = 0
}
} // SchedRW let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
} // hasSideEffects = 0 // FIXME: provide shorter instructions when imm8 == 1
let Uses = [CL] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
// FIXME: provide shorter instructions when imm8 == 1 "rol{b}\t{%cl, $dst|$dst, cl}",
let Uses = [CL] in { [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
"rol{b}\t{%cl, $dst|$dst, cl}", "rol{w}\t{%cl, $dst|$dst, cl}",
[(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>; [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
"rol{w}\t{%cl, $dst|$dst, cl}", "rol{l}\t{%cl, $dst|$dst, cl}",
[(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16; [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
"rol{l}\t{%cl, $dst|$dst, cl}", "rol{q}\t{%cl, $dst|$dst, cl}",
[(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32; [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), }
"rol{q}\t{%cl, $dst|$dst, cl}",
[(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>; def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
} "rol{b}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
"rol{b}\t{$src2, $dst|$dst, $src2}", "rol{w}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>; [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), IIC_SR>, OpSize16;
"rol{w}\t{$src2, $dst|$dst, $src2}", def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
[(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))], "rol{l}\t{$src2, $dst|$dst, $src2}",
IIC_SR>, OpSize16; [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), IIC_SR>, OpSize32;
"rol{l}\t{$src2, $dst|$dst, $src2}", def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))], (ins GR64:$src1, u8imm:$src2),
IIC_SR>, OpSize32; "rol{q}\t{$src2, $dst|$dst, $src2}",
def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
(ins GR64:$src1, u8imm:$src2), IIC_SR>;
"rol{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))], // Rotate by 1
IIC_SR>; def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
"rol{b}\t$dst",
// Rotate by 1 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), IIC_SR>;
"rol{b}\t$dst", def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
[(set GR8:$dst, (rotl GR8:$src1, (i8 1)))], "rol{w}\t$dst",
IIC_SR>; [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), IIC_SR>, OpSize16;
"rol{w}\t$dst", def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
[(set GR16:$dst, (rotl GR16:$src1, (i8 1)))], "rol{l}\t$dst",
IIC_SR>, OpSize16; [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), IIC_SR>, OpSize32;
"rol{l}\t$dst", def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
[(set GR32:$dst, (rotl GR32:$src1, (i8 1)))], "rol{q}\t$dst",
IIC_SR>, OpSize32; [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), IIC_SR>;
"rol{q}\t$dst", } // Constraints = "$src = $dst", SchedRW
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
IIC_SR>; let SchedRW = [WriteShiftLd, WriteRMW] in {
} // Constraints = "$src = $dst", SchedRW let Uses = [CL] in {
def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
let SchedRW = [WriteShiftLd, WriteRMW] in { "rol{b}\t{%cl, $dst|$dst, cl}",
let Uses = [CL] in { [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), IIC_SR>;
"rol{b}\t{%cl, $dst|$dst, cl}", def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
[(store (rotl (loadi8 addr:$dst), CL), addr:$dst)], "rol{w}\t{%cl, $dst|$dst, cl}",
IIC_SR>; [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), IIC_SR>, OpSize16;
"rol{w}\t{%cl, $dst|$dst, cl}", def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
[(store (rotl (loadi16 addr:$dst), CL), addr:$dst)], "rol{l}\t{%cl, $dst|$dst, cl}",
IIC_SR>, OpSize16; [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), IIC_SR>, OpSize32;
"rol{l}\t{%cl, $dst|$dst, cl}", def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)], "rol{q}\t{%cl, $dst|$dst, cl}",
IIC_SR>, OpSize32; [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), IIC_SR>;
"rol{q}\t{%cl, $dst|$dst, cl}", }
[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)], def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1),
IIC_SR>; "rol{b}\t{$src1, $dst|$dst, $src1}",
} [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1), IIC_SR>;
"rol{b}\t{$src1, $dst|$dst, $src1}", def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1),
[(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)], "rol{w}\t{$src1, $dst|$dst, $src1}",
IIC_SR>; [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1), IIC_SR>, OpSize16;
"rol{w}\t{$src1, $dst|$dst, $src1}", def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1),
[(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)], "rol{l}\t{$src1, $dst|$dst, $src1}",
IIC_SR>, OpSize16; [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1), IIC_SR>, OpSize32;
"rol{l}\t{$src1, $dst|$dst, $src1}", def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1),
[(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)], "rol{q}\t{$src1, $dst|$dst, $src1}",
IIC_SR>, OpSize32; [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1), IIC_SR>;
"rol{q}\t{$src1, $dst|$dst, $src1}",
[(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)], // Rotate by 1
IIC_SR>; def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
"rol{b}\t$dst",
// Rotate by 1 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), IIC_SR>;
"rol{b}\t$dst", def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
[(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)], "rol{w}\t$dst",
IIC_SR>; [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), IIC_SR>, OpSize16;
"rol{w}\t$dst", def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
[(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)], "rol{l}\t$dst",
IIC_SR>, OpSize16; [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), IIC_SR>, OpSize32;
"rol{l}\t$dst", def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
[(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)], "rol{q}\t$dst",
IIC_SR>, OpSize32; [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), IIC_SR>;
"rol{q}\t$dst", } // SchedRW
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>; let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
} // SchedRW let Uses = [CL] in {
def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { "ror{b}\t{%cl, $dst|$dst, cl}",
let Uses = [CL] in { [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
"ror{b}\t{%cl, $dst|$dst, cl}", "ror{w}\t{%cl, $dst|$dst, cl}",
[(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>; [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
"ror{w}\t{%cl, $dst|$dst, cl}", "ror{l}\t{%cl, $dst|$dst, cl}",
[(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16; [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
"ror{l}\t{%cl, $dst|$dst, cl}", "ror{q}\t{%cl, $dst|$dst, cl}",
[(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32; [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), }
"ror{q}\t{%cl, $dst|$dst, cl}",
[(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>; def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
} "ror{b}\t{$src2, $dst|$dst, $src2}",
[(set GR8:$dst, (rotr GR8:$src1, (i8 relocImm:$src2)))],
def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2), IIC_SR>;
"ror{b}\t{$src2, $dst|$dst, $src2}", def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
[(set GR8:$dst, (rotr GR8:$src1, (i8 relocImm:$src2)))], "ror{w}\t{$src2, $dst|$dst, $src2}",
IIC_SR>; [(set GR16:$dst, (rotr GR16:$src1, (i8 relocImm:$src2)))],
def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2), IIC_SR>, OpSize16;
"ror{w}\t{$src2, $dst|$dst, $src2}", def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
[(set GR16:$dst, (rotr GR16:$src1, (i8 relocImm:$src2)))], "ror{l}\t{$src2, $dst|$dst, $src2}",
IIC_SR>, OpSize16; [(set GR32:$dst, (rotr GR32:$src1, (i8 relocImm:$src2)))],
def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2), IIC_SR>, OpSize32;
"ror{l}\t{$src2, $dst|$dst, $src2}", def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
[(set GR32:$dst, (rotr GR32:$src1, (i8 relocImm:$src2)))], (ins GR64:$src1, u8imm:$src2),
IIC_SR>, OpSize32; "ror{q}\t{$src2, $dst|$dst, $src2}",
def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), [(set GR64:$dst, (rotr GR64:$src1, (i8 relocImm:$src2)))],
(ins GR64:$src1, u8imm:$src2), IIC_SR>;
"ror{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (rotr GR64:$src1, (i8 relocImm:$src2)))], // Rotate by 1
IIC_SR>; def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
"ror{b}\t$dst",
// Rotate by 1 [(set GR8:$dst, (rotl GR8:$src1, (i8 7)))],
def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), IIC_SR>;
"ror{b}\t$dst", def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
[(set GR8:$dst, (rotl GR8:$src1, (i8 7)))], "ror{w}\t$dst",
IIC_SR>; [(set GR16:$dst, (rotl GR16:$src1, (i8 15)))],
def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), IIC_SR>, OpSize16;
"ror{w}\t$dst", def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
[(set GR16:$dst, (rotl GR16:$src1, (i8 15)))], "ror{l}\t$dst",
IIC_SR>, OpSize16; [(set GR32:$dst, (rotl GR32:$src1, (i8 31)))],
def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), IIC_SR>, OpSize32;
"ror{l}\t$dst", def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
[(set GR32:$dst, (rotl GR32:$src1, (i8 31)))], "ror{q}\t$dst",
IIC_SR>, OpSize32; [(set GR64:$dst, (rotl GR64:$src1, (i8 63)))],
def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), IIC_SR>;
"ror{q}\t$dst", } // Constraints = "$src = $dst", SchedRW
[(set GR64:$dst, (rotl GR64:$src1, (i8 63)))],
IIC_SR>; let SchedRW = [WriteShiftLd, WriteRMW] in {
} // Constraints = "$src = $dst", SchedRW let Uses = [CL] in {
def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
let SchedRW = [WriteShiftLd, WriteRMW] in { "ror{b}\t{%cl, $dst|$dst, cl}",
let Uses = [CL] in { [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), IIC_SR>;
"ror{b}\t{%cl, $dst|$dst, cl}", def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
[(store (rotr (loadi8 addr:$dst), CL), addr:$dst)], "ror{w}\t{%cl, $dst|$dst, cl}",
IIC_SR>; [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), IIC_SR>, OpSize16;
"ror{w}\t{%cl, $dst|$dst, cl}", def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
[(store (rotr (loadi16 addr:$dst), CL), addr:$dst)], "ror{l}\t{%cl, $dst|$dst, cl}",
IIC_SR>, OpSize16; [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), IIC_SR>, OpSize32;
"ror{l}\t{%cl, $dst|$dst, cl}", def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)], "ror{q}\t{%cl, $dst|$dst, cl}",
IIC_SR>, OpSize32; [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), IIC_SR>;
"ror{q}\t{%cl, $dst|$dst, cl}", }
[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)], def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src),
IIC_SR>; "ror{b}\t{$src, $dst|$dst, $src}",
} [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, u8imm:$src), IIC_SR>;
"ror{b}\t{$src, $dst|$dst, $src}", def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src),
[(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)], "ror{w}\t{$src, $dst|$dst, $src}",
IIC_SR>; [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, u8imm:$src), IIC_SR>, OpSize16;
"ror{w}\t{$src, $dst|$dst, $src}", def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src),
[(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)], "ror{l}\t{$src, $dst|$dst, $src}",
IIC_SR>, OpSize16; [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, u8imm:$src), IIC_SR>, OpSize32;
"ror{l}\t{$src, $dst|$dst, $src}", def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src),
[(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)], "ror{q}\t{$src, $dst|$dst, $src}",
IIC_SR>, OpSize32; [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, u8imm:$src), IIC_SR>;
"ror{q}\t{$src, $dst|$dst, $src}",
[(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)], // Rotate by 1
IIC_SR>; def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
"ror{b}\t$dst",
// Rotate by 1 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), IIC_SR>;
"ror{b}\t$dst", def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
[(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)], "ror{w}\t$dst",
IIC_SR>; [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), IIC_SR>, OpSize16;
"ror{w}\t$dst", def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
[(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)], "ror{l}\t$dst",
IIC_SR>, OpSize16; [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), IIC_SR>, OpSize32;
"ror{l}\t$dst", def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
[(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)], "ror{q}\t$dst",
IIC_SR>, OpSize32; [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), IIC_SR>;
"ror{q}\t$dst", } // SchedRW
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
IIC_SR>;
} // SchedRW //===----------------------------------------------------------------------===//
// Double shift instructions (generalizations of rotate)
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Double shift instructions (generalizations of rotate) let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
//===----------------------------------------------------------------------===//
let Uses = [CL] in {
let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in { def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
(ins GR16:$src1, GR16:$src2),
let Uses = [CL] in { "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
(ins GR16:$src1, GR16:$src2), IIC_SHD16_REG_CL>,
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", TB, OpSize16;
[(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))], def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
IIC_SHD16_REG_CL>, (ins GR16:$src1, GR16:$src2),
TB, OpSize16; "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
(ins GR16:$src1, GR16:$src2), IIC_SHD16_REG_CL>,
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", TB, OpSize16;
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))], def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
IIC_SHD16_REG_CL>, (ins GR32:$src1, GR32:$src2),
TB, OpSize16; "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
(ins GR32:$src1, GR32:$src2), IIC_SHD32_REG_CL>, TB, OpSize32;
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))], (ins GR32:$src1, GR32:$src2),
IIC_SHD32_REG_CL>, TB, OpSize32; "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
(ins GR32:$src1, GR32:$src2), IIC_SHD32_REG_CL>, TB, OpSize32;
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))], (ins GR64:$src1, GR64:$src2),
IIC_SHD32_REG_CL>, TB, OpSize32; "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
(ins GR64:$src1, GR64:$src2), IIC_SHD64_REG_CL>,
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", TB;
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))], def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
IIC_SHD64_REG_CL>, (ins GR64:$src1, GR64:$src2),
TB; "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
(ins GR64:$src1, GR64:$src2), IIC_SHD64_REG_CL>,
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", TB;
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))], }
IIC_SHD64_REG_CL>,
TB; let isCommutable = 1 in { // These instructions commute to each other.
} def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
(outs GR16:$dst),
let isCommutable = 1 in { // These instructions commute to each other. (ins GR16:$src1, GR16:$src2, u8imm:$src3),
def SHLD16rri8 : Ii8<0xA4, MRMDestReg, "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
(outs GR16:$dst), [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
(ins GR16:$src1, GR16:$src2, u8imm:$src3), (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
"shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", TB, OpSize16;
[(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
(i8 imm:$src3)))], IIC_SHD16_REG_IM>, (outs GR16:$dst),
TB, OpSize16; (ins GR16:$src1, GR16:$src2, u8imm:$src3),
def SHRD16rri8 : Ii8<0xAC, MRMDestReg, "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
(outs GR16:$dst), [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
(ins GR16:$src1, GR16:$src2, u8imm:$src3), (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
"shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", TB, OpSize16;
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
(i8 imm:$src3)))], IIC_SHD16_REG_IM>, (outs GR32:$dst),
TB, OpSize16; (ins GR32:$src1, GR32:$src2, u8imm:$src3),
def SHLD32rri8 : Ii8<0xA4, MRMDestReg, "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
(outs GR32:$dst), [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
(ins GR32:$src1, GR32:$src2, u8imm:$src3), (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", TB, OpSize32;
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
(i8 imm:$src3)))], IIC_SHD32_REG_IM>, (outs GR32:$dst),
TB, OpSize32; (ins GR32:$src1, GR32:$src2, u8imm:$src3),
def SHRD32rri8 : Ii8<0xAC, MRMDestReg, "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
(outs GR32:$dst), [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
(ins GR32:$src1, GR32:$src2, u8imm:$src3), (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", TB, OpSize32;
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
(i8 imm:$src3)))], IIC_SHD32_REG_IM>, (outs GR64:$dst),
TB, OpSize32; (ins GR64:$src1, GR64:$src2, u8imm:$src3),
def SHLD64rri8 : RIi8<0xA4, MRMDestReg, "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
(outs GR64:$dst), [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
(ins GR64:$src1, GR64:$src2, u8imm:$src3), (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", TB;
[(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
(i8 imm:$src3)))], IIC_SHD64_REG_IM>, (outs GR64:$dst),
TB; (ins GR64:$src1, GR64:$src2, u8imm:$src3),
def SHRD64rri8 : RIi8<0xAC, MRMDestReg, "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
(outs GR64:$dst), [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
(ins GR64:$src1, GR64:$src2, u8imm:$src3), (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", TB;
[(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, }
(i8 imm:$src3)))], IIC_SHD64_REG_IM>, } // Constraints = "$src = $dst", SchedRW
TB;
} let SchedRW = [WriteShiftLd, WriteRMW] in {
} // Constraints = "$src = $dst", SchedRW let Uses = [CL] in {
def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
let SchedRW = [WriteShiftLd, WriteRMW] in { "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
let Uses = [CL] in { [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}", def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
[(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16; [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16; "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}", def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32; [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32; "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), addr:$dst)], IIC_SHD64_MEM_CL>, TB;
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
[(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
addr:$dst)], IIC_SHD64_MEM_CL>, TB; [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), addr:$dst)], IIC_SHD64_MEM_CL>, TB;
"shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}", }
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
addr:$dst)], IIC_SHD64_MEM_CL>, TB; def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
} (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
"shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
def SHLD16mri8 : Ii8<0xA4, MRMDestMem, [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
(outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), (i8 imm:$src3)), addr:$dst)],
"shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", IIC_SHD16_MEM_IM>,
[(store (X86shld (loadi16 addr:$dst), GR16:$src2, TB, OpSize16;
(i8 imm:$src3)), addr:$dst)], def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
IIC_SHD16_MEM_IM>, (outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3),
TB, OpSize16; "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
def SHRD16mri8 : Ii8<0xAC, MRMDestMem, [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
(outs), (ins i16mem:$dst, GR16:$src2, u8imm:$src3), (i8 imm:$src3)), addr:$dst)],
"shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", IIC_SHD16_MEM_IM>,
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2, TB, OpSize16;
(i8 imm:$src3)), addr:$dst)],
IIC_SHD16_MEM_IM>, def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
TB, OpSize16; (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
def SHLD32mri8 : Ii8<0xA4, MRMDestMem, [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
(outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), (i8 imm:$src3)), addr:$dst)],
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", IIC_SHD32_MEM_IM>,
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, TB, OpSize32;
(i8 imm:$src3)), addr:$dst)], def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
IIC_SHD32_MEM_IM>, (outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3),
TB, OpSize32; "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
def SHRD32mri8 : Ii8<0xAC, MRMDestMem, [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
(outs), (ins i32mem:$dst, GR32:$src2, u8imm:$src3), (i8 imm:$src3)), addr:$dst)],
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", IIC_SHD32_MEM_IM>,
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, TB, OpSize32;
(i8 imm:$src3)), addr:$dst)],
IIC_SHD32_MEM_IM>, def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
TB, OpSize32; (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
def SHLD64mri8 : RIi8<0xA4, MRMDestMem, [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
(outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), (i8 imm:$src3)), addr:$dst)],
"shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", IIC_SHD64_MEM_IM>,
[(store (X86shld (loadi64 addr:$dst), GR64:$src2, TB;
(i8 imm:$src3)), addr:$dst)], def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
IIC_SHD64_MEM_IM>, (outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3),
TB; "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
def SHRD64mri8 : RIi8<0xAC, MRMDestMem, [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
(outs), (ins i64mem:$dst, GR64:$src2, u8imm:$src3), (i8 imm:$src3)), addr:$dst)],
"shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", IIC_SHD64_MEM_IM>,
[(store (X86shrd (loadi64 addr:$dst), GR64:$src2, TB;
(i8 imm:$src3)), addr:$dst)], } // SchedRW
IIC_SHD64_MEM_IM>,
TB; } // Defs = [EFLAGS]
} // SchedRW
def ROT32L2R_imm8 : SDNodeXForm<imm, [{
} // Defs = [EFLAGS] // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
return getI8Imm(32 - N->getZExtValue(), SDLoc(N));
def ROT32L2R_imm8 : SDNodeXForm<imm, [{ }]>;
// Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
return getI8Imm(32 - N->getZExtValue(), SDLoc(N)); def ROT64L2R_imm8 : SDNodeXForm<imm, [{
}]>; // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
return getI8Imm(64 - N->getZExtValue(), SDLoc(N));
def ROT64L2R_imm8 : SDNodeXForm<imm, [{ }]>;
// Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
return getI8Imm(64 - N->getZExtValue(), SDLoc(N)); multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
}]>; let hasSideEffects = 0 in {
def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> { !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
let hasSideEffects = 0 in { []>, TAXD, VEX, Sched<[WriteShift]>;
def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2), let mayLoad = 1 in
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
[]>, TAXD, VEX, Sched<[WriteShift]>; (ins x86memop:$src1, u8imm:$src2),
let mayLoad = 1 in !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), []>, TAXD, VEX, Sched<[WriteShiftLd]>;
(ins x86memop:$src1, u8imm:$src2), }
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), }
[]>, TAXD, VEX, Sched<[WriteShiftLd]>;
} multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
} let hasSideEffects = 0 in {
def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> { !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
let hasSideEffects = 0 in { VEX, Sched<[WriteShift]>;
def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), let mayLoad = 1 in
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, def rm : I<0xF7, MRMSrcMem4VOp3,
VEX, Sched<[WriteShift]>; (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
let mayLoad = 1 in !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
def rm : I<0xF7, MRMSrcMem4VOp3, VEX, Sched<[WriteShiftLd,
(outs RC:$dst), (ins x86memop:$src1, RC:$src2), // x86memop:$src1
!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
VEX, Sched<[WriteShiftLd, ReadDefault,
// x86memop:$src1 // RC:$src1
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadAfterLd]>;
ReadDefault, }
// RC:$src1 }
ReadAfterLd]>;
} let Predicates = [HasBMI2] in {
} defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
let Predicates = [HasBMI2] in { defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W;
defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD; // Prefer RORX which is non-destructive and doesn't update EFLAGS.
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W; let AddedComplexity = 10 in {
def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
// Prefer RORX which is non-destructive and doesn't update EFLAGS. (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
let AddedComplexity = 10 in { def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
def : Pat<(rotl GR32:$src, (i8 imm:$shamt)), (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
(RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>; }
def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
(RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>; def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
} (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)), (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
(RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)), // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
(RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>; // immedidate shift, i.e. the following code is considered better
//
// Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not // mov %edi, %esi
// immedidate shift, i.e. the following code is considered better // shl $imm, %esi
// // ... %edi, ...
// mov %edi, %esi //
// shl $imm, %esi // than
// ... %edi, ... //
// // movb $imm, %sil
// than // shlx %sil, %edi, %esi
// // ... %edi, ...
// movb $imm, %sil //
// shlx %sil, %edi, %esi let AddedComplexity = 1 in {
// ... %edi, ... def : Pat<(sra GR32:$src1, GR8:$src2),
// (SARX32rr GR32:$src1,
let AddedComplexity = 1 in { (INSERT_SUBREG
def : Pat<(sra GR32:$src1, GR8:$src2), (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
(SARX32rr GR32:$src1, def : Pat<(sra GR64:$src1, GR8:$src2),
(INSERT_SUBREG (SARX64rr GR64:$src1,
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; (INSERT_SUBREG
def : Pat<(sra GR64:$src1, GR8:$src2), (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
(SARX64rr GR64:$src1,
(INSERT_SUBREG def : Pat<(srl GR32:$src1, GR8:$src2),
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; (SHRX32rr GR32:$src1,
(INSERT_SUBREG
def : Pat<(srl GR32:$src1, GR8:$src2), (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
(SHRX32rr GR32:$src1, def : Pat<(srl GR64:$src1, GR8:$src2),
(INSERT_SUBREG (SHRX64rr GR64:$src1,
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; (INSERT_SUBREG
def : Pat<(srl GR64:$src1, GR8:$src2), (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
(SHRX64rr GR64:$src1,
(INSERT_SUBREG def : Pat<(shl GR32:$src1, GR8:$src2),
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; (SHLX32rr GR32:$src1,
(INSERT_SUBREG
def : Pat<(shl GR32:$src1, GR8:$src2), (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
(SHLX32rr GR32:$src1, def : Pat<(shl GR64:$src1, GR8:$src2),
(INSERT_SUBREG (SHLX64rr GR64:$src1,
(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; (INSERT_SUBREG
def : Pat<(shl GR64:$src1, GR8:$src2), (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
(SHLX64rr GR64:$src1, }
(INSERT_SUBREG
(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>; // Patterns on SARXrm/SHRXrm/SHLXrm are explicitly omitted to favor
} //
// mov (%ecx), %esi
// Patterns on SARXrm/SHRXrm/SHLXrm are explicitly omitted to favor // shl $imm, $esi
// //
// mov (%ecx), %esi // over
// shl $imm, $esi //
// // movb $imm %al
// over // shlx %al, (%ecx), %esi
// //
// movb $imm %al // As SARXrr/SHRXrr/SHLXrr is favored on variable shift, the peephole
// shlx %al, (%ecx), %esi // optimization will fold them into SARXrm/SHRXrm/SHLXrm if possible.
// }
// As SARXrr/SHRXrr/SHLXrr is favored on variable shift, the peephole
// optimization will fold them into SARXrm/SHRXrm/SHLXrm if possible.
}