Hexagon vector store print tracing.

[ronl]

Summary

Add vector store print tracing option for hexagon vector instructions.

[kparzysz]

Looks good with one minor comment.

lib/Target/Hexagon/HexagonVectorPrint.cpp

161

Extra space between "(" and "MBB".

[ronl]

Fixed spacing problem and indentation

[ronl]

submitted.

lib/Target/Hexagon/HexagonVectorPrint.cpp

 
 #define DEBUG_TYPE "hexagon-vector-print"
 
 #include "HexagonTargetMachine.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 
 using namespace llvm;
 
+static cl::opt<bool> TraceHexVectorStoresOnly("trace-hex-vector-stores-only",
+  cl::Hidden, cl::ZeroOrMore, cl::init(false),
+  cl::desc("Enables tracing of vector stores"));
+
 namespace llvm {
   FunctionPass *createHexagonVectorPrint();
   void initializeHexagonVectorPrintPass(PassRegistry&);
 }
 
 
 namespace {
 

 }
 
 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) {
   if (MI.getNumOperands() < 1) return false;
   // Vec load or compute.
   if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef()) {
     Reg = MI.getOperand(0).getReg();
     if (isVecReg(Reg))
-      return true;
+      return !TraceHexVectorStoresOnly;
   }
   // Vec store.
   if (MI.mayStore() && MI.getNumOperands() >= 3 && MI.getOperand(2).isReg()) {
     Reg = MI.getOperand(2).getReg();
     if (isVecReg(Reg))
       return true;
   }
   // Vec store post increment.
bool HexagonVectorPrint::runOnMachineFunction(MachineFunction &Fn) {
   QRI = QST->getRegisterInfo();
   QII = QST->getInstrInfo();
   std::vector<MachineInstr *> VecPrintList;
   for (auto &MBB : Fn)
     for (auto &MI : MBB) {
       if (MI.isBundle()) {
         MachineBasicBlock::instr_iterator MII = MI.getIterator();
         for (++MII; MII != MBB.instr_end() && MII->isInsideBundle(); ++MII) {
-          if (MII->getNumOperands() < 1) continue;
+          if (MII->getNumOperands() < 1)
+            continue;
           unsigned Reg = 0;
           if (getInstrVecReg(*MII, Reg)) {
             VecPrintList.push_back((&*MII));
             DEBUG(dbgs() << "Found vector reg inside bundle \n"; MII->dump());
           }
         }
       } else {
         unsigned Reg = 0;
         if (getInstrVecReg(MI, Reg)) {
           VecPrintList.push_back(&MI);
           DEBUG(dbgs() << "Found vector reg \n"; MI.dump());
         }
       }
     }
 
   Changed = VecPrintList.size() > 0;
-  if (!Changed) return Changed;
+  if (!Changed)
+    return Changed;
 
   for (auto *I : VecPrintList) {
     DebugLoc DL = I->getDebugLoc();
     MachineBasicBlock *MBB = I->getParent();
     DEBUG(dbgs() << "Evaluating V MI\n"; I->dump());
     unsigned Reg = 0;
     if (!getInstrVecReg(*I, Reg))
       llvm_unreachable("Need a vector reg");
     MachineBasicBlock::instr_iterator MII = I->getIterator();
     if (I->isInsideBundle()) {
       DEBUG(dbgs() << "add to end of bundle\n"; I->dump());
-      while (MII->isInsideBundle()) ++MII;
+      while (MBB->instr_end() != MII && MII->isInsideBundle())
+        MII++;
     } else {
       DEBUG(dbgs() << "add after instruction\n"; I->dump());
       MII++;
     }
+    if (MBB->instr_end() == MII)
+      continue;
+
     if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {
       DEBUG(dbgs() << "adding dump for V" << Reg-Hexagon::V0 << '\n');
       addAsmInstr(MBB, Reg, MII, DL, QII, Fn);
     } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {
       DEBUG(dbgs() << "adding dump for W" << Reg-Hexagon::W0 << '\n');
       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,
                   MII, DL, QII, Fn);
       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,

test/CodeGen/Hexagon/v6vec-vprint.ll

 ; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s
 ;   generate .long XXXX which is a vector debug print instruction.
 ; CHECK: .long 0x1dffe0
+; CHECK: .long 0x1dffe0
+; CHECK: .long 0x1dffe0
+; VSTPRINT: .long 0x1dffe0
+; VSTPRINT-NOT: .long 0x1dffe0
 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
 target triple = "hexagon"
 
 ; Function Attrs: nounwind
 define void @do_vecs(i8* nocapture readonly %a, i8* nocapture readonly %b, i8* nocapture %c) #0 {
 entry:
   %0 = bitcast i8* %a to <16 x i32>*
   %1 = load <16 x i32>, <16 x i32>* %0, align 4, !tbaa !1