Fix for PR29010

[myatsina]

Summary

This is a fix for https://llvm.org/bugs/show_bug.cgi?id=29010
Root cause of the bug is that the register class of the machine instruction operand does not fully reflect if this registers that can be allocated.
Both for i386 and x86_64 the operand's register class is VR128RegClass and thus contains xmm0-xmm15, though in i386 we can only use xmm0-xmm8.
In order to get the actual allocable registers of the class we need to use RegisterClassInfo.

[myatsina]

Adding test case

[mkuper]

LGTM, except for a nit in the test.

test/CodeGen/X86/pr29010.ll

1

Why do you need -mcpu? Shouldn't -mattr be enough?

[myatsina]

test/CodeGen/X86/pr29010.ll

1

Copy paste from another test :) I'll remove it

[MatzeB]

Wouldn't it be easier to test MachineRegisterInfo::isAllocatable() instead of constructing a whole RegisterClassInfo object just for this one place?

lib/CodeGen/ExecutionDepsFix.cpp

 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/ADT/PostOrderIterator.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterClassInfo.h"
 #include "llvm/Support/Allocator.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 
 using namespace llvm;
 
class ExeDepsFix : public MachineFunctionPass {
   static char ID;
   SpecificBumpPtrAllocator<DomainValue> Allocator;
   SmallVector<DomainValue*,16> Avail;
 
   const TargetRegisterClass *const RC;
   MachineFunction *MF;
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
+  RegisterClassInfo RegClassInfo;
   std::vector<SmallVector<int, 1>> AliasMap;
   const unsigned NumRegs;
   LiveReg *LiveRegs;
   typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap;
   LiveOutMap LiveOuts;
 
   /// List of undefined register reads in this block in forward order.
   std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
for (MachineOperand &CurrMO : MI->operands()) {
     MO.setReg(CurrMO.getReg());
     return;
   }
 
   // Go over all registers in the register class and find the register with
   // max clearance or clearance higher than Pref.
   unsigned MaxClearance = 0;
   unsigned MaxClearanceReg = OriginalReg;
-  for (auto Reg : OpRC->getRegisters()) {
+  ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
+  for (auto Reg : Order) {
     assert(AliasMap[Reg].size() == 1 &&
            "Reg is expected to be mapped to a single index");
     int RCrx = *regIndices(Reg).begin();
     unsigned Clearance = CurInstr - LiveRegs[RCrx].Def;
     if (Clearance <= MaxClearance)
       continue;
     MaxClearance = Clearance;
     MaxClearanceReg = Reg;

 }
 
 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
   if (skipFunction(*mf.getFunction()))
     return false;
   MF = &mf;
   TII = MF->getSubtarget().getInstrInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
+  RegClassInfo.runOnMachineFunction(mf);
   LiveRegs = nullptr;
   assert(NumRegs == RC->getNumRegs() && "Bad regclass");
 
   DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
                << TRI->getRegClassName(RC) << " **********\n");
 
   // If no relevant registers are used in the function, we can skip it
   // completely.

test/CodeGen/X86/pr29010.ll

+; RUN: llc < %s -mtriple=i386-linux -mattr=+avx -mcpu=haswell | FileCheck %s
+
+; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we we are not creating illegal XMM
+define float @only_xmm0_7(i32 %arg) {
+top:
+  tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()
+  tail call void asm sideeffect "", "~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{dirflag},~{fpsr},~{flags}"()
+  %tmp1 = sitofp i32 %arg to float
+  ret float %tmp1
+;CHECK-LABEL:@only_xmm0_7
+;CHECK: vcvtsi2ssl {{.*}}, {{%xmm[0-7]+}}, {{%xmm[0-7]+}}
+}