[X86] Transform setcc + movzbl into xorl + setcc; ISel tentative

[ab]

Summary

Just a hack to experiment with D21774.

I first tried the naive INSERT_SUBREG, but that ended up generating non-ideal code, like:

	vcomisd	%xmm1, %xmm0
	setae	%cl
	xorl	%eax, %eax
	movb	%cl, %al
	retl

We looked into this with Matthias and Quentin, and I think I got it working, roughly?

Long story short: it's more complicated than it could be because we need to make it friendly to the register coalescer.

If we do the naive INSERT_SUBREG (without any of the glues, nor the custom setcc selection), we end up with:

16B		%vreg1<def> = COPY %XMM1; VR128:%vreg1
32B		%vreg0<def> = COPY %XMM0; VR128:%vreg0
48B		Int_VCOMISDrr %vreg0, %vreg1, %EFLAGS<imp-def>; VR128:%vreg0,%vreg1
64B		%vreg2<def> = SETAEr %EFLAGS<imp-use,kill>; GR8:%vreg2
80B		%vreg3<def> = MOV32ri 0; GR32:%vreg3
96B		%vreg4<def> = COPY %vreg3; GR32_ABCD:%vreg4 GR32:%vreg3
112B		%vreg4:sub_8bit<def> = COPY %vreg2; GR32_ABCD:%vreg4 GR8:%vreg2
128B		%EAX<def> = COPY %vreg4; GR32_ABCD:%vreg4
144B		RET 0, %EAX<kill>

We really want the coalescer to produce:

64B		%vreg4<def> = SETAEr %EFLAGS<imp-use,kill>; GR8:%vreg2
80B		%vreg3<def> = MOV32ri 0; GR32:%vreg3
112B		%vreg4:sub_8bit<def> = COPY %vreg3; GR32_ABCD:%vreg4 GR8:%vreg2

but that's impossible without moving the MOV above the SETcc (which the coalescer doesn't do).

So, instead, we glue the INSERT_SUBREG to the SETcc (itself glued to the EFLAGS copy, because EFLAGS).

A nice consequence of this approach is that the DAG scheduler is the one that ends up deciding where to put the XOR, so that we don't have to care about that and EFLAGS.

WDYT?

[ab]

This has problems with INSERT_SUBREG turning into a real copy; see discussion on D21774.

lib/Target/X86/X86ISelDAGToDAG.cpp

if ((N0.getNode()->getOpcode() == ISD::AND ||
         // one, do not call ReplaceAllUsesWith.
         ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
                     SDValue(NewNode, 0));
         return;
       }
     }
     break;
   }
+
+  case ISD::ZERO_EXTEND: {
+    if (NVT != MVT::i32)
+      break;
+
+    SDValue N0 = Node->getOperand(0);
+    if (N0->getOpcode() != X86ISD::SETCC)
+      break;
+
+    SDValue N01 = N0->getOperand(1);
+
+    // 0 = xor r,r.  This clobbers EFLAGS; let the scheduler figure that out.
+    SDValue Zero = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
+
+    // Select the things below us, if they haven't been selected already.
+    Select(N01.getNode());
+
+    // Copy the flags out whatever's below us.  Produce a glue.
+    SDValue Flags =
+        CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::EFLAGS,
+                             N01, /*Glue=*/SDValue());
+
+    // Pick a SETCC opcode.
+    unsigned SetCCOpc =
+        X86::getSETFromCond((X86::CondCode)N0->getConstantOperandVal(0));
+
+    // Now we can select our node; make abundant use of glue.
+    SDNode *SetCC = CurDAG->getMachineNode(SetCCOpc, SDLoc(N0), MVT::i8,
+                                           MVT::Glue, Flags.getValue(1));
+
+    // And insert it into the zero reg, gluing again.
+    SDNode *NewNode = CurDAG->getMachineNode(
+        X86::INSERT_SUBREG, dl, MVT::i32,
+        {Zero, N0, CurDAG->getTargetConstant(X86::sub_8bit, dl, MVT::i32),
+         SDValue(SetCC, 1)});
+
+    ReplaceUses(N0, SDValue(SetCC, 0));
+    ReplaceUses(SDValue(Node, 0), SDValue(NewNode, 0));
+
+    CurDAG->RemoveDeadNode(N0.getNode());
+    CurDAG->RemoveDeadNode(Node);
+    return;
+  }
+
+
   case ISD::STORE: {
     // Change a chain of {load; incr or dec; store} of the same value into
     // a simple increment or decrement through memory of that value, if the
     // uses of the modified value and its address are suitable.
     // The DEC64m tablegen pattern is currently not able to match the case where
     // the EFLAGS on the original DEC are used. (This also applies to
     // {INC,DEC}X{64,32,16,8}.)
     // We'll need to improve tablegen to allow flags to be transferred from a