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Chuang-Yu Cheng
committedMar 28, 2016
[Power9] Implement new altivec instructions: bcd* series
This patch implements the following altivec instructions: - Decimal Convert From/to National/Zoned/Signed-QWord: bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq. - Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn. - Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr. - Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc. Total 13 instructions Thanks Amehsan's advice! Thanks Kit's great help! Reviewers: hal, nemanja, kbarton, tjablin, amehsan http://reviews.llvm.org/D17838 llvm-svn: 264568
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‎llvm/lib/Target/PowerPC/PPCInstrAltivec.td

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1338,4 +1338,62 @@ def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA),
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// Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword
13391339
def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>;
13401340
def VMUL10ECUQ : VX1_VT5_VA5_VB5< 65, "vmul10ecuq", []>;
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// Decimal Integer Format Conversion Instructions
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// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
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class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
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list<dag> pattern>
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: VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
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!strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
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let Defs = [CR6];
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}
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// [PO VRT EO VRB 1 / XO]
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class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
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list<dag> pattern>
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: VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),
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!strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> {
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let Defs = [CR6];
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let PS = 0;
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}
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// Decimal Convert From/to National/Zoned/Signed-QWord
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def BCDCFNo : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
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def BCDCFZo : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
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def BCDCTNo : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." , []>;
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def BCDCTZo : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
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def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
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def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>;
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// Decimal Copy-Sign/Set-Sign
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let Defs = [CR6] in
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def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
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def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
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// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
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class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
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: VX_RD5_RSp5_PS1_XO9<xo,
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(outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
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!strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
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let Defs = [CR6];
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}
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// [PO VRT VRA VRB 1 / XO]
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class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
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: VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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!strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {
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let Defs = [CR6];
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let PS = 0;
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}
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// Decimal Shift/Unsigned-Shift/Shift-and-Round
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def BCDSo : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
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def BCDUSo : VX_VT5_VA5_VB5_XO9_o <129, "bcdus.", []>;
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def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
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// Decimal (Unsigned) Truncate
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def BCDTRUNCo : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
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def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>;
13411399
} // end HasP9Altivec

‎llvm/lib/Target/PowerPC/PPCInstrFormats.td

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1779,6 +1779,44 @@ class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
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let Inst{22-31} = xo;
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}
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// VX-Form: [PO VRT EO VRB 1 PS XO]
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class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
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dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OOL, IOL, asmstr, itin> {
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bits<5> VD;
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bits<5> VB;
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bit PS;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = eo;
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let Inst{16-20} = VB;
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let Inst{21} = 1;
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let Inst{22} = PS;
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let Inst{23-31} = xo;
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}
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// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
1802+
class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
1803+
InstrItinClass itin, list<dag> pattern>
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: I<4, OOL, IOL, asmstr, itin> {
1805+
bits<5> VD;
1806+
bits<5> VA;
1807+
bits<5> VB;
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bit PS;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = VA;
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let Inst{16-20} = VB;
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let Inst{21} = 1;
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let Inst{22} = PS;
1817+
let Inst{23-31} = xo;
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}
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17821820
// Z23-Form (used by QPX)
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class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>

‎llvm/lib/Target/PowerPC/README_P9.txt

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,36 @@ Altivec:
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VX1_Int_Ty<577, "vmul10euq", int_ppc_altivec_vmul10euq, v1i128>;
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VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
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- Decimal Convert From/to National/Zoned/Signed-QWord:
144+
bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq.
145+
. Use instrinstics:
146+
(set v1i128:$vD, (int_ppc_altivec_bcdcfno v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcdcfzo v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcdctno v1i128:$vB))
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(set v1i128:$vD, (int_ppc_altivec_bcdctzo v1i128:$vB, i1:$PS))
150+
(set v1i128:$vD, (int_ppc_altivec_bcdcfsqo v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcdctsqo v1i128:$vB))
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153+
- Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn.
154+
. Use instrinstics:
155+
(set v1i128:$vD, (int_ppc_altivec_bcdcpsgno v1i128:$vA, v1i128:$vB))
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(set v1i128:$vD, (int_ppc_altivec_bcdsetsgno v1i128:$vB, i1:$PS))
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- Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr.
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. Use instrinstics:
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(set v1i128:$vD, (int_ppc_altivec_bcdso v1i128:$vA, v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB))
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(set v1i128:$vD, (int_ppc_altivec_bcdsro v1i128:$vA, v1i128:$vB, i1:$PS))
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. Note! Their VA is accessed only 1 byte, i.e. VA.byte[7]
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- Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc.
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. Use instrinstics:
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(set v1i128:$vD, (int_ppc_altivec_bcdso v1i128:$vA, v1i128:$vB, i1:$PS))
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(set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB))
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. Note! Their VA is accessed only 2 byte, i.e. VA.hword[3] (VA.bit[48:63])
172+
143173
VSX:
144174
- QP Copy Sign: xscpsgnqp
145175
. Similar to xscpsgndp

‎llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

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Original file line numberDiff line numberDiff line change
@@ -837,3 +837,42 @@
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# CHECK: vmul10ecuq 2, 3, 4
839839
0x10 0x43 0x20 0x41
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# CHECK: bcdcfn. 27, 31, 1
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0x13 0x67 0xff 0x81
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# CHECK: bcdcfz. 27, 31, 1
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0x13 0x66 0xff 0x81
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# CHECK: bcdctn. 27, 31
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0x13 0x65 0xfd 0x81
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# CHECK: bcdctz. 27, 31, 1
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0x13 0x64 0xff 0x81
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# CHECK: bcdcfsq. 27, 31, 1
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0x13 0x62 0xff 0x81
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# CHECK: bcdctsq. 27, 31
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0x13 0x60 0xfd 0x81
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# CHECK: bcdcpsgn. 27, 31, 7
860+
0x13 0x7f 0x3b 0x41
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# CHECK: bcdsetsgn. 27, 31, 1
863+
0x13 0x7f 0xff 0x81
864+
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# CHECK: bcds. 27, 31, 7, 1
866+
0x13 0x7f 0x3e 0xc1
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868+
# CHECK: bcdus. 27, 31, 7
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0x13 0x7f 0x3c 0x81
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# CHECK: bcdsr. 27, 31, 7, 1
872+
0x13 0x7f 0x3f 0xc1
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874+
# CHECK: bcdtrunc. 27, 31, 7, 1
875+
0x13 0x7f 0x3f 0x01
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877+
# CHECK: bcdutrunc. 27, 31, 7
878+
0x13 0x7f 0x3d 0x41

‎llvm/test/MC/PowerPC/ppc64-encoding-vmx.s

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -932,3 +932,50 @@
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# CHECK-BE: vmul10ecuq 2, 3, 4 # encoding: [0x10,0x43,0x20,0x41]
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# CHECK-LE: vmul10ecuq 2, 3, 4 # encoding: [0x41,0x20,0x43,0x10]
934934
vmul10ecuq 2, 3, 4
935+
936+
# Decimal Convert From/to National/Zoned/Signed-QWord
937+
# CHECK-BE: bcdcfn. 27, 31, 1 # encoding: [0x13,0x67,0xff,0x81]
938+
# CHECK-LE: bcdcfn. 27, 31, 1 # encoding: [0x81,0xff,0x67,0x13]
939+
bcdcfn. 27, 31, 1
940+
# CHECK-BE: bcdcfz. 27, 31, 1 # encoding: [0x13,0x66,0xff,0x81]
941+
# CHECK-LE: bcdcfz. 27, 31, 1 # encoding: [0x81,0xff,0x66,0x13]
942+
bcdcfz. 27, 31, 1
943+
# CHECK-BE: bcdctn. 27, 31 # encoding: [0x13,0x65,0xfd,0x81]
944+
# CHECK-LE: bcdctn. 27, 31 # encoding: [0x81,0xfd,0x65,0x13]
945+
bcdctn. 27, 31
946+
# CHECK-BE: bcdctz. 27, 31, 1 # encoding: [0x13,0x64,0xff,0x81]
947+
# CHECK-LE: bcdctz. 27, 31, 1 # encoding: [0x81,0xff,0x64,0x13]
948+
bcdctz. 27, 31, 1
949+
# CHECK-BE: bcdcfsq. 27, 31, 1 # encoding: [0x13,0x62,0xff,0x81]
950+
# CHECK-LE: bcdcfsq. 27, 31, 1 # encoding: [0x81,0xff,0x62,0x13]
951+
bcdcfsq. 27, 31, 1
952+
# CHECK-BE: bcdctsq. 27, 31 # encoding: [0x13,0x60,0xfd,0x81]
953+
# CHECK-LE: bcdctsq. 27, 31 # encoding: [0x81,0xfd,0x60,0x13]
954+
bcdctsq. 27, 31
955+
956+
# Decimal Copy-Sign/Set-Sign
957+
# CHECK-BE: bcdcpsgn. 27, 31, 7 # encoding: [0x13,0x7f,0x3b,0x41]
958+
# CHECK-LE: bcdcpsgn. 27, 31, 7 # encoding: [0x41,0x3b,0x7f,0x13]
959+
bcdcpsgn. 27, 31, 7
960+
# CHECK-BE: bcdsetsgn. 27, 31, 1 # encoding: [0x13,0x7f,0xff,0x81]
961+
# CHECK-LE: bcdsetsgn. 27, 31, 1 # encoding: [0x81,0xff,0x7f,0x13]
962+
bcdsetsgn. 27, 31, 1
963+
964+
# Decimal Shift/Unsigned-Shift/Shift-and-Round
965+
# CHECK-BE: bcds. 27, 31, 7, 1 # encoding: [0x13,0x7f,0x3e,0xc1]
966+
# CHECK-LE: bcds. 27, 31, 7, 1 # encoding: [0xc1,0x3e,0x7f,0x13]
967+
bcds. 27, 31, 7, 1
968+
# CHECK-BE: bcdus. 27, 31, 7 # encoding: [0x13,0x7f,0x3c,0x81]
969+
# CHECK-LE: bcdus. 27, 31, 7 # encoding: [0x81,0x3c,0x7f,0x13]
970+
bcdus. 27, 31, 7
971+
# CHECK-BE: bcdsr. 27, 31, 7, 1 # encoding: [0x13,0x7f,0x3f,0xc1]
972+
# CHECK-LE: bcdsr. 27, 31, 7, 1 # encoding: [0xc1,0x3f,0x7f,0x13]
973+
bcdsr. 27, 31, 7, 1
974+
975+
# Decimal (Unsigned) Truncate
976+
# CHECK-BE: bcdtrunc. 27, 31, 7, 1 # encoding: [0x13,0x7f,0x3f,0x01]
977+
# CHECK-LE: bcdtrunc. 27, 31, 7, 1 # encoding: [0x01,0x3f,0x7f,0x13]
978+
bcdtrunc. 27, 31, 7, 1
979+
# CHECK-BE: bcdutrunc. 27, 31, 7 # encoding: [0x13,0x7f,0x3d,0x41]
980+
# CHECK-LE: bcdutrunc. 27, 31, 7 # encoding: [0x41,0x3d,0x7f,0x13]
981+
bcdutrunc. 27, 31, 7

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