[Power9] Implement new altivec instructions: bcd* series

[cycheng]

Summary

This patch implements the following altivec instructions:

• Decimal Convert From/to National/Zoned/Signed-QWord bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq.
• Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn.
• Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr.
• Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc.

Total 13 instructions

[amehsan]

lib/Target/PowerPC/PPCInstrAltivec.td

1283

You can change the comment to "CR6 is set" to make it more understandable. Wording of ISA for bcdcfn. is: "CR field 6 is set to reflect src compared to zero".

1318

same here.

[kbarton]

LGTM

[cycheng]

Committed r264568

lib/Target/PowerPC/PPCInstrAltivec.td

1283

Done! Thanks : )

lib/Target/PowerPC/PPCInstrAltivec.td

 def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
 def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
 
 // Vector Insert Element Instructions
 def VINSERTB : VX1_VT5_UIM5_VB5<781, "vinsertb", []>;
 def VINSERTH : VX1_VT5_UIM5_VB5<845, "vinserth", []>;
 def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
 def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
+
+// Decimal Integer Format Conversion Instructions
+
+// [PO VRT EO VRB 1 PS XO], "_o" means CR6 is reflected.
+class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
+                               list<dag> pattern>
+  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
+                        !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
+  let Defs = [CR6];
+}
+
+// [PO VRT EO VRB 1 / XO]
+class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
+                           list<dag> pattern>
+  : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),
+                           !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> {
+  let Defs = [CR6];
+  let PS = 0;
+}
+
+// Decimal Convert From/to National/Zoned/Signed-QWord
+def BCDCFNo  : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
+def BCDCFZo  : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
+def BCDCTNo  : VX_VT5_EO5_VB5_XO9_o    <5, 385, "bcdctn." , []>;
+def BCDCTZo  : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
+def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
+def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o    <0, 385, "bcdctsq.", []>;
+
+class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>
+  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+             !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>;
+
+// Decimal Copy-Sign/Set-Sign
+let Defs = [CR6] in
+def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
+
+def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
+
+// [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is reflected.
+class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
+  : VX_RD5_RSp5_PS1_XO9<xo,
+                   (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
+                   !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
+  let Defs = [CR6];
+}
+
+// [PO VRT VRA VRB 1 / XO]
+class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
+  : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                        !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {
+  let Defs = [CR6];
+  let PS = 0;
+}
+
+// Decimal Shift/Unsigned-Shift/Shift-and-Round
+def BCDSo :  VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
+def BCDUSo : VX_VT5_VA5_VB5_XO9_o    <129, "bcdus.", []>;
+def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
+
+// Decimal (Unsigned) Truncate
+def BCDTRUNCo :  VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
+def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o    <321, "bcdutrunc.", []>;
+
 } // end HasP9Altivec

lib/Target/PowerPC/PPCInstrFormats.td

class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
   let Pattern = pattern;
   
   let Inst{6-10}  = RST;
   let Inst{11-15} = DS_RA{18-14};  // Register #
   let Inst{16-29} = DS_RA{13-0};   // Displacement.
   let Inst{30-31} = xo;
 }
 
-
 // 1.7.6 X-Form
 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
                       InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> RST;
   bits<5> A;
   bits<5> B;
 
class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
   
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
   let Inst{16-20} = VB;
   let Inst{21}    = RC;
   let Inst{22-31} = xo;
 }
 
+// VX-Form: [PO VRT EO VRB 1 PS XO]
+class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo,
+                             dag OOL, dag IOL, string asmstr,
+                             InstrItinClass itin, list<dag> pattern>
+  : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VB;
+  bit PS;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = eo;
+  let Inst{16-20} = VB;
+  let Inst{21}    = 1;
+  let Inst{22}    = PS;
+  let Inst{23-31} = xo;
+}
+
+// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO]
+class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
+                          InstrItinClass itin, list<dag> pattern>
+  : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VA;
+  bits<5> VB;
+  bit PS;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = VA;
+  let Inst{16-20} = VB;
+  let Inst{21}    = 1;
+  let Inst{22}    = PS;
+  let Inst{23-31} = xo;
+}
+
 // Z23-Form (used by QPX)
 class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> FRT;
   bits<5> FRA;
   bits<5> FRB;
   bits<2> idx;

lib/Target/PowerPC/README_P9.txt

. Use instrinstics:
     (set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
 
 - Vector Insert Element Instructions: vinsertb vinsertd vinserth vinsertw
     (set v16i8:$vD, (int_ppc_altivec_vinsertb v16i8:$vA, imm:$UIMM))
     (set v8i16:$vD, (int_ppc_altivec_vinsertd v8i16:$vA, imm:$UIMM))
     (set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
     (set v2i64:$vD, (int_ppc_altivec_vinsertw v2i64:$vA, imm:$UIMM))
 
+- Decimal Convert From/to National/Zoned/Signed-QWord:
+  bcdcfn. bcdcfz. bcdctn. bcdctz. bcdcfsq. bcdctsq.
+  . Use instrinstics:
+    (set v1i128:$vD, (int_ppc_altivec_bcdcfno  v1i128:$vB, i1:$PS))
+    (set v1i128:$vD, (int_ppc_altivec_bcdcfzo  v1i128:$vB, i1:$PS))
+    (set v1i128:$vD, (int_ppc_altivec_bcdctno  v1i128:$vB))
+    (set v1i128:$vD, (int_ppc_altivec_bcdctzo  v1i128:$vB, i1:$PS))
+    (set v1i128:$vD, (int_ppc_altivec_bcdcfsqo v1i128:$vB, i1:$PS))
+    (set v1i128:$vD, (int_ppc_altivec_bcdctsqo v1i128:$vB))
+
+- Decimal Copy-Sign/Set-Sign: bcdcpsgn. bcdsetsgn.
+  . Use instrinstics:
+    (set v1i128:$vD, (int_ppc_altivec_bcdcpsgno v1i128:$vA, v1i128:$vB))
+    (set v1i128:$vD, (int_ppc_altivec_bcdsetsgno v1i128:$vB, i1:$PS))
+
+- Decimal Shift/Unsigned-Shift/Shift-and-Round: bcds. bcdus. bcdsr.
+  . Use instrinstics:
+    (set v1i128:$vD, (int_ppc_altivec_bcdso  v1i128:$vA, v1i128:$vB, i1:$PS))
+    (set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB))
+    (set v1i128:$vD, (int_ppc_altivec_bcdsro v1i128:$vA, v1i128:$vB, i1:$PS))
+
+  . Note! Their VA is accessed only 1 byte, i.e. VA.byte[7]
+
+- Decimal (Unsigned) Truncate: bcdtrunc. bcdutrunc.
+  . Use instrinstics:
+    (set v1i128:$vD, (int_ppc_altivec_bcdso  v1i128:$vA, v1i128:$vB, i1:$PS))
+    (set v1i128:$vD, (int_ppc_altivec_bcduso v1i128:$vA, v1i128:$vB))
+
+  . Note! Their VA is accessed only 2 byte, i.e. VA.hword[3] (VA.bit[48:63])
+
 VSX:
 
 - QP Compare Ordered/Unordered: xscmpoqp xscmpuqp
   . ref: XSCMPUDP
       def XSCMPUDP : XX3Form_1<60, 35,
                                (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
                                "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>;
 

test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x4e 0x1b 0x4d
 
 # CHECK: vinsertw 2, 3, 12
 0x10 0x4c 0x1b 0x8d
 
 # CHECK: vinsertd 2, 3, 8
 0x10 0x48 0x1b 0xcd
 
+# CHECK: bcdcfn. 27, 31, 1
+0x13 0x67 0xff 0x81
+
+# CHECK: bcdcfz. 27, 31, 1
+0x13 0x66 0xff 0x81
+
+# CHECK: bcdctn. 27, 31
+0x13 0x65 0xfd 0x81
+
+# CHECK: bcdctz. 27, 31, 1
+0x13 0x64 0xff 0x81
+
+# CHECK: bcdcfsq. 27, 31, 1
+0x13 0x62 0xff 0x81
+
+# CHECK: bcdctsq. 27, 31
+0x13 0x60 0xfd 0x81
+
+# CHECK: bcdcpsgn. 27, 31, 7
+0x13 0x7f 0x3b 0x41
+
+# CHECK: bcdsetsgn. 27, 31, 1
+0x13 0x7f 0xff 0x81
+
+# CHECK: bcds. 27, 31, 7, 1
+0x13 0x7f 0x3e 0xc1
+
+# CHECK: bcdus. 27, 31, 7
+0x13 0x7f 0x3c 0x81
+
+# CHECK: bcdsr. 27, 31, 7, 1
+0x13 0x7f 0x3f 0xc1
+
+# CHECK: bcdtrunc. 27, 31, 7, 1
+0x13 0x7f 0x3f 0x01
+
+# CHECK: bcdutrunc. 27, 31, 7
+0x13 0x7f 0x3d 0x41

test/MC/PowerPC/ppc64-encoding-vmx.s

# CHECK-LE: vinserth 2, 3, 14               # encoding: [0x4d,0x1b,0x4e,0x10]
             vinserth 2, 3, 14
 # CHECK-BE: vinsertw 2, 3, 12               # encoding: [0x10,0x4c,0x1b,0x8d]
 # CHECK-LE: vinsertw 2, 3, 12               # encoding: [0x8d,0x1b,0x4c,0x10]
             vinsertw 2, 3, 12
 # CHECK-BE: vinsertd 2, 3, 8                # encoding: [0x10,0x48,0x1b,0xcd]
 # CHECK-LE: vinsertd 2, 3, 8                # encoding: [0xcd,0x1b,0x48,0x10]
             vinsertd 2, 3, 8
 
+# Decimal Convert From/to National/Zoned/Signed-QWord
+# CHECK-BE: bcdcfn. 27, 31, 1                  # encoding: [0x13,0x67,0xff,0x81]
+# CHECK-LE: bcdcfn. 27, 31, 1                  # encoding: [0x81,0xff,0x67,0x13]
+            bcdcfn. 27, 31, 1
+# CHECK-BE: bcdcfz. 27, 31, 1                  # encoding: [0x13,0x66,0xff,0x81]
+# CHECK-LE: bcdcfz. 27, 31, 1                  # encoding: [0x81,0xff,0x66,0x13]
+            bcdcfz. 27, 31, 1
+# CHECK-BE: bcdctn. 27, 31                     # encoding: [0x13,0x65,0xfd,0x81]
+# CHECK-LE: bcdctn. 27, 31                     # encoding: [0x81,0xfd,0x65,0x13]
+            bcdctn. 27, 31
+# CHECK-BE: bcdctz. 27, 31, 1                  # encoding: [0x13,0x64,0xff,0x81]
+# CHECK-LE: bcdctz. 27, 31, 1                  # encoding: [0x81,0xff,0x64,0x13]
+            bcdctz. 27, 31, 1
+# CHECK-BE: bcdcfsq. 27, 31, 1                 # encoding: [0x13,0x62,0xff,0x81]
+# CHECK-LE: bcdcfsq. 27, 31, 1                 # encoding: [0x81,0xff,0x62,0x13]
+            bcdcfsq. 27, 31, 1
+# CHECK-BE: bcdctsq. 27, 31                    # encoding: [0x13,0x60,0xfd,0x81]
+# CHECK-LE: bcdctsq. 27, 31                    # encoding: [0x81,0xfd,0x60,0x13]
+            bcdctsq. 27, 31
+
+# Decimal Copy-Sign/Set-Sign
+# CHECK-BE: bcdcpsgn. 27, 31, 7                # encoding: [0x13,0x7f,0x3b,0x41]
+# CHECK-LE: bcdcpsgn. 27, 31, 7                # encoding: [0x41,0x3b,0x7f,0x13]
+            bcdcpsgn. 27, 31, 7
+# CHECK-BE: bcdsetsgn. 27, 31, 1               # encoding: [0x13,0x7f,0xff,0x81]
+# CHECK-LE: bcdsetsgn. 27, 31, 1               # encoding: [0x81,0xff,0x7f,0x13]
+            bcdsetsgn. 27, 31, 1
+
+# Decimal Shift/Unsigned-Shift/Shift-and-Round
+# CHECK-BE: bcds. 27, 31, 7, 1                 # encoding: [0x13,0x7f,0x3e,0xc1]
+# CHECK-LE: bcds. 27, 31, 7, 1                 # encoding: [0xc1,0x3e,0x7f,0x13]
+            bcds. 27, 31, 7, 1
+# CHECK-BE: bcdus. 27, 31, 7                   # encoding: [0x13,0x7f,0x3c,0x81]
+# CHECK-LE: bcdus. 27, 31, 7                   # encoding: [0x81,0x3c,0x7f,0x13]
+            bcdus. 27, 31, 7
+# CHECK-BE: bcdsr. 27, 31, 7, 1                # encoding: [0x13,0x7f,0x3f,0xc1]
+# CHECK-LE: bcdsr. 27, 31, 7, 1                # encoding: [0xc1,0x3f,0x7f,0x13]
+            bcdsr. 27, 31, 7, 1
+
+# Decimal (Unsigned) Truncate
+# CHECK-BE: bcdtrunc. 27, 31, 7, 1             # encoding: [0x13,0x7f,0x3f,0x01]
+# CHECK-LE: bcdtrunc. 27, 31, 7, 1             # encoding: [0x01,0x3f,0x7f,0x13]
+            bcdtrunc. 27, 31, 7, 1
+# CHECK-BE: bcdutrunc. 27, 31, 7               # encoding: [0x13,0x7f,0x3d,0x41]
+# CHECK-LE: bcdutrunc. 27, 31, 7               # encoding: [0x41,0x3d,0x7f,0x13]
+            bcdutrunc. 27, 31, 7