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Vasileios KalintirisVasileios Kalintiris
Vasileios Kalintiris
authored and
Vasileios Kalintiris
committedNov 6, 2015
[mips] Define patterns for the atomic_{load,store}_{8,16,32,64} nodes.
Summary: Without these patterns we would generate a complete LL/SC sequence. This would be problematic for memory regions marked as WRITE-only or READ-only, as the instructions LL/SC would read/write to the protected memory regions correspondingly. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14397 llvm-svn: 252293
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‎llvm/lib/Target/Mips/Mips64InstrInfo.td

+12
Original file line numberDiff line numberDiff line change
@@ -546,6 +546,18 @@ def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst
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(BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
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}
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// Atomic load patterns.
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def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
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def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>;
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def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>;
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def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>;
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// Atomic store patterns.
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def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>;
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def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>;
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def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>;
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def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -391,10 +391,10 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
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if (!Subtarget.isGP64bit()) {
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setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
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}
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setInsertFencesForAtomic(true);
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‎llvm/lib/Target/Mips/MipsInstrInfo.td

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@@ -2083,6 +2083,16 @@ let AddedComplexity = 40 in {
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}
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}
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// Atomic load patterns.
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def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>;
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def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>;
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def : MipsPat<(atomic_load_32 addr:$a), (LW addr:$a)>;
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// Atomic store patterns.
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def : MipsPat<(atomic_store_8 addr:$a, GPR32:$v), (SB GPR32:$v, addr:$a)>;
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def : MipsPat<(atomic_store_16 addr:$a, GPR32:$v), (SH GPR32:$v, addr:$a)>;
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def : MipsPat<(atomic_store_32 addr:$a, GPR32:$v), (SW GPR32:$v, addr:$a)>;
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//===----------------------------------------------------------------------===//
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// Floating Point Support
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//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/Mips/atomicSCr6.ll

-32
This file was deleted.

‎llvm/test/CodeGen/Mips/llvm-ir/atomicrmx.ll

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
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; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s | \
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; RUN: FileCheck %s -check-prefix=CHK32
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; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s | \
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; RUN: FileCheck %s -check-prefix=CHK64
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@a = common global i32 0, align 4
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@b = common global i64 0, align 8
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define i32 @ll_sc(i32 signext %x) {
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; CHK32-LABEL: ll_sc
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;CHK32: LL_R6
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;CHK32: SC_R6
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%1 = atomicrmw add i32* @a, i32 %x monotonic
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ret i32 %1
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}
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define i64 @lld_scd(i64 signext %x) {
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; CHK64-LABEL: lld_scd
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;CHK64: LLD_R6
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;CHK64: SCD_R6
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%1 = atomicrmw add i64* @b, i64 %x monotonic
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ret i64 %1
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}

‎llvm/test/CodeGen/Mips/llvm-ir/load-atomic.ll

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@@ -0,0 +1,42 @@
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; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64
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; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64
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define i8 @load_i8(i8* %ptr) {
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; ALL-LABEL: load_i8
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; ALL: lb $2, 0($4)
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; ALL: sync
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%val = load atomic i8, i8* %ptr acquire, align 1
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ret i8 %val
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}
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define i16 @load_i16(i16* %ptr) {
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; ALL-LABEL: load_i16
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; ALL: lh $2, 0($4)
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; ALL: sync
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%val = load atomic i16, i16* %ptr acquire, align 2
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ret i16 %val
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}
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define i32 @load_i32(i32* %ptr) {
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; ALL-LABEL: load_i32
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; ALL: lw $2, 0($4)
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; ALL: sync
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%val = load atomic i32, i32* %ptr acquire, align 4
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ret i32 %val
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}
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define i64 @load_i64(i64* %ptr) {
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; M64-LABEL: load_i64
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; M64: ld $2, 0($4)
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; M64: sync
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%val = load atomic i64, i64* %ptr acquire, align 8
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ret i64 %val
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}

‎llvm/test/CodeGen/Mips/llvm-ir/store-atomic.ll

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@@ -0,0 +1,42 @@
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; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64
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; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \
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; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64
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define void @store_i8(i8* %ptr, i8 signext %v) {
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; ALL-LABEL: store_i8
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; ALL: sync
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; ALL: sb $5, 0($4)
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store atomic i8 %v, i8* %ptr release, align 1
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ret void
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}
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define void @store_i16(i16* %ptr, i16 signext %v) {
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; ALL-LABEL: store_i16
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; ALL: sync
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; ALL: sh $5, 0($4)
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store atomic i16 %v, i16* %ptr release, align 2
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ret void
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}
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define void @store_i32(i32* %ptr, i32 signext %v) {
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; ALL-LABEL: store_i32
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; ALL: sync
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; ALL: sw $5, 0($4)
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store atomic i32 %v, i32* %ptr release, align 4
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ret void
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}
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define void @store_i64(i64* %ptr, i64 %v) {
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; M64-LABEL: store_i64
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; M64: sync
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; M64: sd $5, 0($4)
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store atomic i64 %v, i64* %ptr release, align 8
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ret void
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}

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