Without these patterns we would generate a complete LL/SC sequence.
This would be problematic for memory regions marked as WRITE-only or
READ-only, as the instructions LL/SC would read/write to the protected
memory regions correspondingly.
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Details
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Diff Detail
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- rL LLVM
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LGTM with some minor changes
lib/Target/Mips/MipsISelLowering.cpp | ||
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394 ↗ | (On Diff #39419) | This ought to be a check for N32/N64 but I'm planning to change the predicate itself later so no need to change this now. |
lib/Target/Mips/MipsInstrInfo.td | ||
2087–2092 ↗ | (On Diff #39419) | The multiclass doesn't provide a noticeable benefit here. It's just distributing the RC argument. I'd prefer loads/stores to be defined separately. |
test/CodeGen/Mips/atomic-load-store.ll | ||
1 ↗ | (On Diff #39419) | (filename): This kind of minimal single-statement test is what I had in mind when creating the test/CodeGen/Mips/llvm-ir directory. Could you split the load/stores into test/CodeGen/Mips/llvm-ir/{store,load}-atomic.ll |
test/CodeGen/Mips/atomicSCr6.ll | ||
1 ↗ | (On Diff #39419) | (filename): Similarly here but with atomicrmx.ll Thanks for tidying this test. |
Comment Actions
This bug is resolved in rL252293. In detail it is explained in comment: https://dmz-portal.mips.com/bugz/show_bug.cgi?id=2231