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author
Quentin Colombet
committedAug 20, 2014
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property. This is a follow-up of r215394 and r215404, which respectively introduces the isRegSequence property and uses it for ARM. Thanks to the property introduced by the previous commits, this patch is able to optimize the following sequence: vmov d0, r2, r3 vmov d1, r0, r1 vmov r0, s0 vmov r1, s2 udiv r0, r1, r0 vmov r1, s1 vmov r2, s3 udiv r1, r2, r1 vmov.32 d16[0], r0 vmov.32 d16[1], r1 vmov r0, r1, d16 bx lr into: udiv r0, r0, r2 udiv r1, r1, r3 vmov.32 d16[0], r0 vmov.32 d16[1], r1 vmov r0, r1, d16 bx lr This patch refactors how the copy optimizations are done in the peephole optimizer. Prior to this patch, we had one copy-related optimization that replaced a copy or bitcast by a generic, more suitable (in terms of register file), copy. With this patch, the peephole optimizer features two copy-related optimizations: 1. One for rewriting generic copies to generic copies: PeepholeOptimizer::optimizeCoalescableCopy. 2. One for replacing non-generic copies with generic copies: PeepholeOptimizer::optimizeUncoalescableCopy. The goals of these two optimizations are slightly different: one rewrite the operand of the instruction (#1), the other kills off the non-generic instruction and replace it by a (sequence of) generic instruction(s). Both optimizations rely on the ValueTracker introduced in r212100. The ValueTracker has been refactored to use the information from the TargetInstrInfo for non-generic instruction. As part of the refactoring, we switched the tracking from the index of the definition to the actual register (virtual or physical). This one change is to provide better consistency with register related APIs and to ease the use of the TargetInstrInfo. Moreover, this patch introduces a new helper class CopyRewriter used to ease the rewriting of generic copies (i.e., #1). Finally, this patch adds a dead code elimination pass right after the peephole optimizer to get rid of dead code that may appear after rewriting. This is related to <rdar://problem/12702965>. Review: http://reviews.llvm.org/D4874 llvm-svn: 216088
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llvmorg-21-initllvmorg-3.5.2-rc1
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3 files changed

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lines changed
 

‎llvm/lib/CodeGen/Passes.cpp

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@@ -607,6 +607,9 @@ void TargetPassConfig::addMachineSSAOptimization() {
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printAndVerify("After Machine LICM, CSE and Sinking passes");
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addPass(&PeepholeOptimizerID);
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// Clean-up the dead code that may have been generated by peephole
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// rewriting.
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addPass(&DeadMachineInstructionElimID);
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printAndVerify("After codegen peephole optimization pass");
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}
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‎llvm/lib/CodeGen/PeepholeOptimizer.cpp

+607-169
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‎llvm/test/CodeGen/ARM/adv-copy-opt.ll

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; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=true | FileCheck -check-prefix=NOOPT --check-prefix=CHECK %s
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; RUN: llc -O1 -mtriple=armv7s-apple-ios -mcpu=swift < %s -disable-adv-copy-opt=false | FileCheck -check-prefix=OPT --check-prefix=CHECK %s
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; CHECK-LABEL: simpleVectorDiv
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; ABI: %A => r0, r1.
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; %B => r2, r3
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; ret => r0, r1
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; We want to compute:
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; r0 = r0 / r2
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; r1 = r1 / r3
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;
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; NOOPT: vmov [[B:d[0-9]+]], r2, r3
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; NOOPT-NEXT: vmov [[A:d[0-9]+]], r0, r1
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; Move the low part of B into a register.
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; Unfortunately, we cannot express that the 's' register is the low
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; part of B, i.e., sIdx == BIdx x 2. E.g., B = d1, B_low = s2.
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; NOOPT-NEXT: vmov [[B_LOW:r[0-9]+]], s{{[0-9]+}}
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; NOOPT-NEXT: vmov [[A_LOW:r[0-9]+]], s{{[0-9]+}}
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; NOOPT-NEXT: udiv [[RES_LOW:r[0-9]+]], [[A_LOW]], [[B_LOW]]
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; NOOPT-NEXT: vmov [[B_HIGH:r[0-9]+]], s{{[0-9]+}}
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; NOOPT-NEXT: vmov [[A_HIGH:r[0-9]+]], s{{[0-9]+}}
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; NOOPT-NEXT: udiv [[RES_HIGH:r[0-9]+]], [[A_HIGH]], [[B_HIGH]]
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; NOOPT-NEXT: vmov.32 [[RES:d[0-9]+]][0], [[RES_LOW]]
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; NOOPT-NEXT: vmov.32 [[RES]][1], [[RES_HIGH]]
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; NOOPT-NEXT: vmov r0, r1, [[RES]]
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; NOOPT-NEXT: bx lr
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;
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; OPT-NOT: vmov
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; OPT: udiv [[RES_LOW:r[0-9]+]], r0, r2
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; OPT-NEXT: udiv [[RES_HIGH:r[0-9]+]], r1, r3
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; OPT-NEXT: vmov.32 [[RES:d[0-9]+]][0], [[RES_LOW]]
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; OPT-NEXT: vmov.32 [[RES]][1], [[RES_HIGH]]
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; OPT-NEXT: vmov r0, r1, [[RES]]
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; OPT-NEXT: bx lr
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define <2 x i32> @simpleVectorDiv(<2 x i32> %A, <2 x i32> %B) nounwind {
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entry:
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%div = udiv <2 x i32> %A, %B
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ret <2 x i32> %div
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}

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