[Hexagon] Remove dead constant assignment in hardware loop pass

[bcahoon]

Summary

After converting a loop to a hardware loop, the pass should remove any unnecessary instructions from the old compare-and-branch code. This patch removes a dead constant assignment that was used in the compare instruction.

llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp

if (!MDT->properlyDominates(DefBB, Header))
       return nullptr;
     OldInsts.push_back(MRI->getVRegDef(R));
   }
   if (EndValue->isReg()) {
     unsigned R = EndValue->getReg();
     MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
     if (!MDT->properlyDominates(DefBB, Header))
       return nullptr;
+    OldInsts.push_back(MRI->getVRegDef(R));
   }
 
   return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
 }
 
 /// \brief Helper function that returns the expression that represents the
 /// number of times a loop iterates.  The function takes the operands that
 /// represent the loop start value, loop end value, and induction value.
 /// Based upon these operands, the function attempts to compute the trip count.
 CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
                                                const MachineOperand *Start,
                                                const MachineOperand *End,
                                                unsigned IVReg,
                                                int64_t IVBump,
                                                Comparison::Kind Cmp) const {
   // Cannot handle comparison EQ, i.e. while (A == B).
   if (Cmp == Comparison::EQ)
     return nullptr;
 
   // Check if either the start or end values are an assignment of an immediate.
   // If so, use the immediate value rather than the register.
   if (Start->isReg()) {
     const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
-    if (StartValInstr && StartValInstr->getOpcode() == Hexagon::A2_tfrsi)
+    if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
+                          StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
       Start = &StartValInstr->getOperand(1);
   }
   if (End->isReg()) {
     const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
-    if (EndValInstr && EndValInstr->getOpcode() == Hexagon::A2_tfrsi)
+    if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
+                        EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
       End = &EndValInstr->getOperand(1);
   }
 
   if (!Start->isReg() && !Start->isImm())
     return nullptr;
   if (!End->isReg() && !End->isImm())
     return nullptr;
 
for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
       const TargetRegisterClass *RC = MRI->getRegClass(PR);
       unsigned NewPR = MRI->createVirtualRegister(RC);
       NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
 
       // Copy all non-latch operands of a header's PHI node to the newly
       // created PHI node in the preheader.
       for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
         unsigned PredR = PN->getOperand(i).getReg();
+        unsigned PredRSub = PN->getOperand(i).getSubReg();
         MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
         if (PredB == Latch)
           continue;
 
-        NewPN->addOperand(MachineOperand::CreateReg(PredR, false));
+        MachineOperand MO = MachineOperand::CreateReg(PredR, false);
+        MO.setSubReg(PredRSub);
+        NewPN->addOperand(MO);
         NewPN->addOperand(MachineOperand::CreateMBB(PredB));
       }
 
       // Remove copied operands from the old PHI node and add the value
       // coming from the preheader's PHI.
       for (int i = PN->getNumOperands()-2; i > 0; i -= 2) {
         MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
         if (PredB != Latch) {

llvm/trunk/test/CodeGen/Hexagon/hwloop-ph-deadcode.ll

+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s
+
+; Test that there is no redundant register assignment in the hardware loop
+; preheader.
+
+; CHECK-NOT: r{{.*}} = #5
+
+@g = external global i32
+
+define void @foo() #0 {
+entry:
+  br i1 undef, label %if.end38, label %for.body
+
+for.body:
+  %loopIdx.051 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  store i32 1, i32* @g, align 4
+  %inc = add i32 %loopIdx.051, 1
+  %cmp9 = icmp ult i32 %inc, 5
+  br i1 %cmp9, label %for.body, label %if.end38
+
+if.end38:
+  ret void
+}