[mips] [IAS] Add support for LASym with identical source and destination register operands.

[tomatabacu]

Summary

In this case, we're supposed to load the address of the symbol in AT and then ADDu it with the source register and
put it in the destination register.

[tomatabacu]

Rebased.

[tomatabacu]

Rebased on top of D9523.

[dsanders]

LGTM with the repetition removed.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2029–2030

Instead of repeating `UseAT ? ATReg : DstReg`, why not define a new variable for the temporary register to use?

[tomatabacu]

Addressed review nit.
Rebased (for Sean Bruno's convenience).

[dsanders]

Toma tells me he's going to untangle this patch from the patches it depends on. The problem is that a couple of those patches have uncovered badly broken MCExpr simplification which is blocking them.

[tomatabacu]

Replaced the UseAT variable with its corresponding condition, as it was being used only once.
Put the "SrcReg != Mips::NoRegister" condition in a variable, as it is now used twice.
Shortened the name of IntermediateDstReg to TmpReg.
Rebased on top of the new D9523 and D9348.
Removed unnecessary dependencies on other patches.

[tomatabacu]

Moved ATReg inside the if block, as it is not used again after that.

[tomatabacu]

Rebased.

I think this is the final version of this patch, as all of its dependencies have been committed.
Daniel, could take another look at this please ?

[dsanders]

LGTM. Thanks

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

bool MipsAsmParser::loadAndAddSymbolAddress(
 
   MCInst tmpInst;
   const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymExpr);
   const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::create(
       &Symbol->getSymbol(), MCSymbolRefExpr::VK_Mips_ABS_HI, getContext());
   const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::create(
       &Symbol->getSymbol(), MCSymbolRefExpr::VK_Mips_ABS_LO, getContext());
 
+  bool UseSrcReg = SrcReg != Mips::NoRegister;
+
+  unsigned TmpReg = DstReg;
+  if (UseSrcReg && (DstReg == SrcReg)) {
+    // At this point we need AT to perform the expansions and we exit if it is
+    // not available.
+    unsigned ATReg = getATReg(IDLoc);
+    if (!ATReg)
+      return true;
+    TmpReg = ATReg;
+  }
+
   if (!Is32BitSym) {
     // If it's a 64-bit architecture, expand to:
     // la d,sym => lui  d,highest(sym)
     //             ori  d,d,higher(sym)
     //             dsll d,d,16
     //             ori  d,d,hi16(sym)
     //             dsll d,d,16
     //             ori  d,d,lo16(sym)
     const MCSymbolRefExpr *HighestExpr = MCSymbolRefExpr::create(
         &Symbol->getSymbol(), MCSymbolRefExpr::VK_Mips_HIGHEST, getContext());
     const MCSymbolRefExpr *HigherExpr = MCSymbolRefExpr::create(
         &Symbol->getSymbol(), MCSymbolRefExpr::VK_Mips_HIGHER, getContext());
 
     tmpInst.setOpcode(Mips::LUi);
-    tmpInst.addOperand(MCOperand::createReg(DstReg));
+    tmpInst.addOperand(MCOperand::createReg(TmpReg));
     tmpInst.addOperand(MCOperand::createExpr(HighestExpr));
     Instructions.push_back(tmpInst);
 
-    createLShiftOri<0>(MCOperand::createExpr(HigherExpr), DstReg, SMLoc(),
+    createLShiftOri<0>(MCOperand::createExpr(HigherExpr), TmpReg, SMLoc(),
                        Instructions);
-    createLShiftOri<16>(MCOperand::createExpr(HiExpr), DstReg, SMLoc(),
+    createLShiftOri<16>(MCOperand::createExpr(HiExpr), TmpReg, SMLoc(),
                         Instructions);
-    createLShiftOri<16>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
+    createLShiftOri<16>(MCOperand::createExpr(LoExpr), TmpReg, SMLoc(),
                         Instructions);
   } else {
     // Otherwise, expand to:
     // la d,sym => lui  d,hi16(sym)
     //             ori  d,d,lo16(sym)
     tmpInst.setOpcode(Mips::LUi);
-    tmpInst.addOperand(MCOperand::createReg(DstReg));
+    tmpInst.addOperand(MCOperand::createReg(TmpReg));
     tmpInst.addOperand(MCOperand::createExpr(HiExpr));
     Instructions.push_back(tmpInst);
 
-    createLShiftOri<0>(MCOperand::createExpr(LoExpr), DstReg, SMLoc(),
+    createLShiftOri<0>(MCOperand::createExpr(LoExpr), TmpReg, SMLoc(),
                        Instructions);
   }
 
-  if (SrcReg != Mips::NoRegister)
-    createAddu(DstReg, DstReg, SrcReg, Instructions);
+  if (UseSrcReg)
+    createAddu(DstReg, TmpReg, SrcReg, Instructions);
 
   return false;
 }
 
 bool MipsAsmParser::expandUncondBranchMMPseudo(
     MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) {
   assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
          "unexpected number of operands");

test/MC/Mips/mips-expansions.s

 # CHECK: ori     $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35]
 # CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
   la $8, symbol($9)
 # CHECK: lui  $8, %hi(symbol)        # encoding: [A,A,0x08,0x3c]
 # CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
 # CHECK: ori  $8, $8, %lo(symbol)    # encoding: [A,A,0x08,0x35]
 # CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
 # CHECK: addu $8, $8, $9             # encoding: [0x21,0x40,0x09,0x01]
+  la $8, symbol($8)
+# CHECK: lui  $1, %hi(symbol)        # encoding: [A,A,0x01,0x3c]
+# CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
+# CHECK: ori  $1, $1, %lo(symbol)    # encoding: [A,A,0x21,0x34]
+# CHECK:                             #   fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16
+# CHECK: addu $8, $1, $8             # encoding: [0x21,0x40,0x28,0x00]
 
 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
   .set noat
   lw $10, symbol($4)
 # CHECK: lui     $10, %hi(symbol)        # encoding: [A,A,0x0a,0x3c]
 # CHECK:                                 #   fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16
 # CHECK: addu    $10, $10, $4            # encoding: [0x21,0x50,0x44,0x01]
 # CHECK: lw      $10, %lo(symbol)($10)   # encoding: [A,A,0x4a,0x8d]