Add intrinsics and SDNodes for umin, umax, smin and smax.

[jmolloy]

Summary

Add intrinsics and SDNodes for umin, umax, smin and smax.

This adds new intrinsics for signed/unsigned min/max. The intention is that
these intrinsics will be matched late in CGP (in a followup patch).

This patch adds the nodes, as well as legalization support and sets them to
be "expand" for all targets.

Sanity of generated code is tested on AArch64.

[reames]

Everything seems reasonable to me, but I'm not familiar enough with all the parts touched to sign off.

Also, you should make sure this gets highlighted on llvmdev. Summarize the current proposal, link to the review thread discussion, and give folks a chance to see the changes proposed. It's possible there's something we've missed when thinking about the trade offs.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

5461

Mild preference to pull out an LHS variable since you're using it twice. Same for each case below.

[Gerolf]

docs/LangRef.rst

9569

Is there are way to distinguish between user and compiler generated intrinsic? And assert on user?

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

77

just MINMAX(N) would be consistent with (many :-) other Promote... interfaces.

[jmolloy]

This got LGTM'd on the list and was committed.

docs/LangRef.rst

 
 Examples:
 """""""""
 
 .. code-block:: llvm
 
       %r2 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) ; yields float:r2 = (a * b) + c
 
+'``llvm.umin.*``' and ``llvm.smin.*`` Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic. You can use ``llvm.umin`` or ``llvm.smin``
+on any integer bit width.
+
+.. code-block:: llvm
+
+      declare i8 @llvm.umin.i8(i8 %a, i8 %b)
+      declare i16 @llvm.umin.i16(i16 %a, i16 %b)
+      declare i32 @llvm.umin.i32(i32 %a, i32 %b)
+      declare i64 @llvm.umin.i64(i64 %a, i64 %b)
+      declare i8 @llvm.smin.i8(i8 %a, i8 %b)
+      declare i16 @llvm.smin.i16(i16 %a, i16 %b)
+      declare i32 @llvm.smin.i32(i32 %a, i32 %b)
+      declare i64 @llvm.smin.i64(i64 %a, i64 %b)
+
+
+Overview:
+"""""""""
+
+The ``llvm.umin`` intrinsic returns the minimum of the two operands,
+treating them both as unsigned integers.
+
+The ``llvm.smin`` intrinsic returns the minimum of the two operands,
+treating them both as signed integers.
+
+.. note::
+
+    These intrinsics are primarily used during late-stage code generation.
+
+    They are generated by the compiler for the compiler and it is not 
+    recommended for users to create them manually. Identity and constant
+    folding will not do as good a job with these intrinsics as with
+    the canonical, and recommended, ``icmp; select`` sequence given below.
+
+Arguments:
+""""""""""
+
+Both intrinsics take two integer arguments of the same bitwidth.
+
+Semantics:
+""""""""""
+
+The expression::
+
+    call i8 @llvm.umin.i8(i8 %a, i8 %b)
+
+is equivalent to::
+
+    %1 = icmp ult i8 %a, %b
+    %2 = select i1 %1, i8 %a, i8 %b
+
+Similarly the expression::
+
+    call i8 @llvm.smin.i8(i8 %a, i8 %b)
+
+is equivalent to::
+
+    %1 = icmp slt i8 %a, %b
+    %2 = select i1 %1, i8 %a, i8 %b
+
+Examples:
+"""""""""
+
+.. code-block:: llvm
+
+      %1 = call i8 @llvm.smin.i8(i8 42, i8 -24) ; Yields -24
+      %1 = call i8 @llvm.umin.i8(i8 42, i8 -24) ; Yields 42
+
+
+'``llvm.umax.*``' and ``llvm.smax.*`` Intrinsics
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Syntax:
+"""""""
+This is an overloaded intrinsic. You can use ``llvm.umax`` or ``llvm.smax``
+on any integer bit width.
+
+.. code-block:: llvm
+
+      declare i8 @llvm.umax.i8(i8 %a, i8 %b)
+      declare i16 @llvm.umax.i16(i16 %a, i16 %b)
+      declare i32 @llvm.umax.i32(i32 %a, i32 %b)
+      declare i64 @llvm.umax.i64(i64 %a, i64 %b)
+      declare i8 @llvm.smax.i8(i8 %a, i8 %b)
+      declare i16 @llvm.smax.i16(i16 %a, i16 %b)
+      declare i32 @llvm.smax.i32(i32 %a, i32 %b)
+      declare i64 @llvm.smax.i64(i64 %a, i64 %b)
+
+
+Overview:
+"""""""""
+
+The ``llvm.umax`` intrinsic returns the maximum of the two operands,
+treating them both as unsigned integers.
+
+The ``llvm.smax`` intrinsic returns the maximum of the two operands,
+treating them both as signed integers.
+
+.. note::
+
+    These intrinsics are primarily used during late-stage code generation.
+
+    They are generated by the compiler for the compiler and it is not 
+    recommended for users to create them manually. Identity and constant
+    folding will not do as good a job with these intrinsics as with
+    the canonical, and recommended, ``icmp; select`` sequence given below.
+
+Arguments:
+""""""""""
+
+Both intrinsics take two integer arguments of the same bitwidth.
+
+Semantics:
+""""""""""
+
+The expression::
+
+    call i8 @llvm.umax.i8(i8 %a, i8 %b)
+
+is equivalent to::
+
+    %1 = icmp ugt i8 %a, %b
+    %2 = select i1 %1, i8 %a, i8 %b
+
+Similarly the expression::
+
+    call i8 @llvm.smax.i8(i8 %a, i8 %b)
+
+is equivalent to::
+
+    %1 = icmp sgt i8 %a, %b
+    %2 = select i1 %1, i8 %a, i8 %b
+
+Examples:
+"""""""""
+
+.. code-block:: llvm
+
+      %1 = call i8 @llvm.smax.i8(i8 42, i8 -24) ; Yields 42
+      %1 = call i8 @llvm.umax.i8(i8 42, i8 -24) ; Yields -24
+
 Half Precision Floating Point Intrinsics
 ----------------------------------------
 
 For most target platforms, half precision floating point is a
 storage-only format. This means that it is a dense encoding (in memory)
 but does not support computation in the format.
 
 This means that code must first load the half-precision floating point

include/llvm/CodeGen/ISDOpcodes.h

enum NodeType {
     /// than the vector element type, and is implicitly truncated to it.
     SCALAR_TO_VECTOR,
 
     /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
     /// producing an unsigned/signed value of type i[2*N], then return the top
     /// part.
     MULHU, MULHS,
 
+    /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
+    /// integers.
+    SMIN, SMAX, UMIN, UMAX,
+
     /// Bitwise operators - logical and, logical or, logical xor.
     AND, OR, XOR,
 
     /// Shift and rotation operations.  After legalization, the type of the
     /// shift amount is known to be TLI.getShiftAmountTy().  Before legalization
     /// the shift amount can be any type, but care must be taken to ensure it is
     /// large enough.  TLI.getShiftAmountTy() is i8 on some targets, but before
     /// legalization, types like i1024 can occur and i8 doesn't have enough bits

include/llvm/IR/Intrinsics.td

 let Properties = [IntrNoMem] in {
   def int_fma  : Intrinsic<[llvm_anyfloat_ty],
                            [LLVMMatchType<0>, LLVMMatchType<0>,
                             LLVMMatchType<0>]>;
   def int_fmuladd : Intrinsic<[llvm_anyfloat_ty],
                               [LLVMMatchType<0>, LLVMMatchType<0>,
                                LLVMMatchType<0>]>;
 
+  def int_umin : Intrinsic<[llvm_anyint_ty],
+                           [LLVMMatchType<0>, LLVMMatchType<0>]>;
+  def int_smin : Intrinsic<[llvm_anyint_ty],
+                           [LLVMMatchType<0>, LLVMMatchType<0>]>;
+  def int_umax : Intrinsic<[llvm_anyint_ty],
+                           [LLVMMatchType<0>, LLVMMatchType<0>]>;
+  def int_smax : Intrinsic<[llvm_anyint_ty],
+                           [LLVMMatchType<0>, LLVMMatchType<0>]>;
+
   // These functions do not read memory, but are sensitive to the
   // rounding mode. LLVM purposely does not model changes to the FP
   // environment so they can be treated as readnone.
   def int_sqrt : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_powi : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty]>;
   def int_sin  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_cos  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
   def int_pow  : Intrinsic<[llvm_anyfloat_ty],

include/llvm/Target/TargetSelectionDAG.td

 def addc       : SDNode<"ISD::ADDC"      , SDTIntBinOp,
                         [SDNPCommutative, SDNPOutGlue]>;
 def adde       : SDNode<"ISD::ADDE"      , SDTIntBinOp,
                         [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
 def subc       : SDNode<"ISD::SUBC"      , SDTIntBinOp,
                         [SDNPOutGlue]>;
 def sube       : SDNode<"ISD::SUBE"      , SDTIntBinOp,
                         [SDNPOutGlue, SDNPInGlue]>;
+def smin       : SDNode<"ISD::SMIN"      , SDTIntBinOp>;
+def smax       : SDNode<"ISD::SMAX"      , SDTIntBinOp>;
+def umin       : SDNode<"ISD::UMIN"      , SDTIntBinOp>;
+def umax       : SDNode<"ISD::UMAX"      , SDTIntBinOp>;
 
 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
 def bswap      : SDNode<"ISD::BSWAP"      , SDTIntUnaryOp>;
 def ctlz       : SDNode<"ISD::CTLZ"       , SDTIntUnaryOp>;
 def cttz       : SDNode<"ISD::CTTZ"       , SDTIntUnaryOp>;
 def ctpop      : SDNode<"ISD::CTPOP"      , SDTIntUnaryOp>;
 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

case ISD::FABS: {
     Tmp2 = DAG.getConstantFP(0.0, VT);
     Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
                         Tmp1, Tmp2, ISD::SETUGT);
     Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
     Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
     Results.push_back(Tmp1);
     break;
   }
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::UMIN:
+  case ISD::UMAX: {
+    // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
+    ISD::CondCode Pred;
+    switch (Node->getOpcode()) {
+    default: llvm_unreachable("How did we get here?");
+    case ISD::SMAX: Pred = ISD::SETGT; break;
+    case ISD::SMIN: Pred = ISD::SETLT; break;
+    case ISD::UMAX: Pred = ISD::SETUGT; break;
+    case ISD::UMIN: Pred = ISD::SETULT; break;
+    }
+    Tmp1 = Node->getOperand(0);
+    Tmp2 = Node->getOperand(1);
+    Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
+    Results.push_back(Tmp1);
+    break;
+  }
+    
   case ISD::FMINNUM:
     Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
                                       RTLIB::FMIN_F80, RTLIB::FMIN_F128,
                                       RTLIB::FMIN_PPCF128));
     break;
   case ISD::FMAXNUM:
     Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
                                       RTLIB::FMAX_F80, RTLIB::FMAX_F128,

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

#endif
   case ISD::EXTRACT_VECTOR_ELT:
                          Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
   case ISD::LOAD:        Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
   case ISD::MLOAD:       Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
   case ISD::SELECT:      Res = PromoteIntRes_SELECT(N); break;
   case ISD::VSELECT:     Res = PromoteIntRes_VSELECT(N); break;
   case ISD::SELECT_CC:   Res = PromoteIntRes_SELECT_CC(N); break;
   case ISD::SETCC:       Res = PromoteIntRes_SETCC(N); break;
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::UMIN:
+  case ISD::UMAX:        Res = PromoteIntRes_MINMAX(N, N->getOpcode()); break;
   case ISD::SHL:         Res = PromoteIntRes_SHL(N); break;
   case ISD::SIGN_EXTEND_INREG:
                          Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
   case ISD::SRA:         Res = PromoteIntRes_SRA(N); break;
   case ISD::SRL:         Res = PromoteIntRes_SRL(N); break;
   case ISD::TRUNCATE:    Res = PromoteIntRes_TRUNCATE(N); break;
   case ISD::UNDEF:       Res = PromoteIntRes_UNDEF(N); break;
   case ISD::VAARG:       Res = PromoteIntRes_VAARG(N); break;
SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
   // Promote all the way up to the canonical SetCC type.
   Mask = PromoteTargetBoolean(Mask, OpTy);
   SDValue LHS = GetPromotedInteger(N->getOperand(1));
   SDValue RHS = GetPromotedInteger(N->getOperand(2));
   return DAG.getNode(ISD::VSELECT, SDLoc(N),
                      LHS.getValueType(), Mask, LHS, RHS);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_MINMAX(SDNode *N, unsigned Opcode) {
+  SDValue LHS = GetPromotedInteger(N->getOperand(0));
+  SDValue RHS = GetPromotedInteger(N->getOperand(1));
+  return DAG.getNode(Opcode, SDLoc(N),
+                     LHS.getValueType(), LHS, RHS);
+}
+
 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
   SDValue LHS = GetPromotedInteger(N->getOperand(2));
   SDValue RHS = GetPromotedInteger(N->getOperand(3));
   return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
                      LHS.getValueType(), N->getOperand(0),
                      N->getOperand(1), LHS, RHS, N->getOperand(4));
 }
 

lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   SDValue PromoteIntRes_SRA(SDNode *N);
   SDValue PromoteIntRes_SRL(SDNode *N);
   SDValue PromoteIntRes_TRUNCATE(SDNode *N);
   SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
   SDValue PromoteIntRes_UDIV(SDNode *N);
   SDValue PromoteIntRes_UNDEF(SDNode *N);
   SDValue PromoteIntRes_VAARG(SDNode *N);
   SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
+  SDValue PromoteIntRes_MINMAX(SDNode *N, unsigned Opcode);
 
   // Integer Operand Promotion.
   bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
   SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
   SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
   SDValue PromoteIntOp_BITCAST(SDNode *N);
   SDValue PromoteIntOp_BUILD_PAIR(SDNode *N);
   SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);

lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
   case ISD::FFLOOR:
   case ISD::FP_ROUND:
   case ISD::FP_EXTEND:
   case ISD::FMA:
   case ISD::SIGN_EXTEND_INREG:
   case ISD::ANY_EXTEND_VECTOR_INREG:
   case ISD::SIGN_EXTEND_VECTOR_INREG:
   case ISD::ZERO_EXTEND_VECTOR_INREG:
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::UMIN:
+  case ISD::UMAX:
     QueryType = Node->getValueType(0);
     break;
   case ISD::FP_ROUND_INREG:
     QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
     break;
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     QueryType = Node->getOperand(0).getValueType();

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
   case ISD::OR:
   case ISD::XOR:
   case ISD::SHL:
   case ISD::SRA:
   case ISD::SRL:
   case ISD::UREM:
   case ISD::SREM:
   case ISD::FREM:
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::UMIN:
+  case ISD::UMAX:
     SplitVecRes_BinOp(N, Lo, Hi);
     break;
   case ISD::FMA:
     SplitVecRes_TernaryOp(N, Lo, Hi);
     break;
   }
 
   // If Lo/Hi is null, the sub-method took care of registering results etc.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

case Intrinsic::framerecover: {
     SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
     setValue(&I, Add);
 
     return nullptr;
   }
   case Intrinsic::eh_begincatch:
   case Intrinsic::eh_endcatch:
     llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
+  case Intrinsic::smin:
+    setValue(&I, DAG.getNode(ISD::SMIN, sdl,
+                             getValue(I.getArgOperand(0)).getValueType(),
+                             getValue(I.getArgOperand(0)),
+                             getValue(I.getArgOperand(1))));
+    return nullptr;
+  case Intrinsic::smax:
+    setValue(&I, DAG.getNode(ISD::SMAX, sdl,
+                             getValue(I.getArgOperand(0)).getValueType(),
+                             getValue(I.getArgOperand(0)),
+                             getValue(I.getArgOperand(1))));
+    return nullptr;
+  case Intrinsic::umin:
+    setValue(&I, DAG.getNode(ISD::UMIN, sdl,
+                             getValue(I.getArgOperand(0)).getValueType(),
+                             getValue(I.getArgOperand(0)),
+                             getValue(I.getArgOperand(1))));
+    return nullptr;
+  case Intrinsic::umax:
+    setValue(&I, DAG.getNode(ISD::UMAX, sdl,
+                             getValue(I.getArgOperand(0)).getValueType(),
+                             getValue(I.getArgOperand(0)),
+                             getValue(I.getArgOperand(1))));
+    return nullptr;
+
   }
 }
 
 std::pair<SDValue, SDValue>
 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
                                     MachineBasicBlock *LandingPad) {
   MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
   MCSymbol *BeginLabel = nullptr;

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

#endif
   case ISD::FMUL:                       return "fmul";
   case ISD::FDIV:                       return "fdiv";
   case ISD::FMA:                        return "fma";
   case ISD::FMAD:                       return "fmad";
   case ISD::FREM:                       return "frem";
   case ISD::FCOPYSIGN:                  return "fcopysign";
   case ISD::FGETSIGN:                   return "fgetsign";
   case ISD::FPOW:                       return "fpow";
+  case ISD::SMIN:                       return "smin";
+  case ISD::SMAX:                       return "smax";
+  case ISD::UMIN:                       return "umin";
+  case ISD::UMAX:                       return "umax";
 
   case ISD::FPOWI:                      return "fpowi";
   case ISD::SETCC:                      return "setcc";
   case ISD::SELECT:                     return "select";
   case ISD::VSELECT:                    return "vselect";
   case ISD::SELECT_CC:                  return "select_cc";
   case ISD::INSERT_VECTOR_ELT:          return "insert_vector_elt";
   case ISD::EXTRACT_VECTOR_ELT:         return "extract_vector_elt";

lib/CodeGen/TargetLoweringBase.cpp

for (MVT VT : MVT::all_valuetypes()) {
     setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
 
     // These operations default to expand.
     setOperationAction(ISD::FGETSIGN, VT, Expand);
     setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
     setOperationAction(ISD::FMINNUM, VT, Expand);
     setOperationAction(ISD::FMAXNUM, VT, Expand);
     setOperationAction(ISD::FMAD, VT, Expand);
+    setOperationAction(ISD::SMIN, VT, Expand);
+    setOperationAction(ISD::SMAX, VT, Expand);
+    setOperationAction(ISD::UMIN, VT, Expand);
+    setOperationAction(ISD::UMAX, VT, Expand);
 
     // These library functions default to expand.
     setOperationAction(ISD::FROUND, VT, Expand);
 
     // These operations default to expand for vector types.
     if (VT.isVector()) {
       setOperationAction(ISD::FCOPYSIGN, VT, Expand);
       setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);

test/CodeGen/AArch64/maxmin-expand.ll

+; RUN: llc < %s -mtriple=aarch64-linux-gnu -O3 | FileCheck %s
+
+; Check that expansion of llvm.[su]{min,max} intrinsics produces sensible code.
+
+; CHECK-LABEL: test_umin_i8
+; CHECK: cmp
+; CHECK-NEXT: csel
+; CHECK-NEXT: ret
+define i8 @test_umin_i8(i8 %a, i8 %b) {
+  %1 = call i8 @llvm.umin.i8(i8 %a, i8 %b)
+  ret i8 %1
+}
+
+; CHECK: cmp
+; CHECK-NEXT: csel
+; CHECK-NEXT: ret
+define i16 @test_smin_i16(i16 %a, i16 %b) {
+  %1 = call i16 @llvm.smin.i16(i16 %a, i16 %b)
+  ret i16 %1
+}
+
+; CHECK: cmp
+; CHECK-NEXT: csel
+; CHECK-NEXT: ret
+define i32 @test_smax_i32(i32 %a, i32 %b) {
+  %1 = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+  ret i32 %1
+}
+
+; CHECK: cmp
+; CHECK-NEXT: csel
+; CHECK-NEXT: ret
+define i64 @test_umax_i64(i64 %a, i64 %b) {
+  %1 = call i64 @llvm.umax.i64(i64 %a, i64 %b)
+  ret i64 %1
+}
+
+declare i8 @llvm.umin.i8(i8, i8)
+declare i16 @llvm.smin.i16(i16, i16)
+declare i32 @llvm.smax.i32(i32, i32)
+declare i64 @llvm.umax.i64(i64, i64)