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Differential D8290

Remove unused complex patterns for addressing modes on Hexagon
ClosedPublic

Authored by kparzysz on Mar 12 2015, 6:57 AM.

Details

Reviewers
colinl
Summary

Remove all the SelectAddrXYZ functions.

Diff Detail

Repository
rL LLVM

Event Timeline

kparzysz updated this revision to Diff 21827.Mar 12 2015, 6:57 AM
kparzysz retitled this revision from to Remove unused complex patterns for addressing modes on Hexagon.
kparzysz updated this object.
kparzysz edited the test plan for this revision. (Show Details)
kparzysz added a reviewer: colinl.
kparzysz set the repository for this revision to rL LLVM.
kparzysz added a subscriber: Unknown Object (MLST).
colinl accepted this revision.Mar 12 2015, 8:48 AM
colinl edited edge metadata.

LGTM

This revision is now accepted and ready to land.Mar 12 2015, 8:48 AM
kparzysz closed this revision.Mar 13 2015, 1:14 PM

Revision Contents

PathSize
lib/
Target/
Hexagon/
8 lines
738 lines
13 lines
17 lines
13 lines
33 lines
4 lines
test/
CodeGen/
Hexagon/
2 lines

Diff 21827

lib/Target/Hexagon/Hexagon.td

Context not available.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Hexagon Instruction Predicate Definitions. // Hexagon Instruction Predicate Definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def HasV5T : Predicate<"Subtarget->hasV5TOps()">; def HasV5T : Predicate<"HST.hasV5TOps()">;
def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; def NoV5T : Predicate<"!HST.hasV5TOps()">;
def UseMEMOP : Predicate<"Subtarget->useMemOps()">; def UseMEMOP : Predicate<"HST.useMemOps()">;
def IEEERndNearV5T : Predicate<"Subtarget->modeIEEERndNear()">; def IEEERndNearV5T : Predicate<"HST.modeIEEERndNear()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Classes used for relation maps. // Classes used for relation maps.
Context not available.

lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

Context not available.
/// ///
namespace { namespace {
class HexagonDAGToDAGISel : public SelectionDAGISel { class HexagonDAGToDAGISel : public SelectionDAGISel {
/// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can const HexagonTargetMachine& HTM;
/// make the right decision when generating code for different targets. const HexagonSubtarget &HST;
const HexagonSubtarget *Subtarget;
// Keep a reference to HexagonTargetMachine.
const HexagonTargetMachine& TM;
public: public:
explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine, explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
CodeGenOpt::Level OptLevel) CodeGenOpt::Level OptLevel)
: SelectionDAGISel(targetmachine, OptLevel), TM(targetmachine) { : SelectionDAGISel(tm, OptLevel), HTM(tm),
HST(tm.getSubtarget<HexagonSubtarget>()) {
initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry()); initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
} }
SDNode *Select(SDNode *N) override; SDNode *Select(SDNode *N) override;
// Complex Pattern Selectors. // Complex Pattern Selectors.
inline bool foldGlobalAddress(SDValue &N, SDValue &R);
inline bool foldGlobalAddressGP(SDValue &N, SDValue &R);
bool foldGlobalAddressImpl(SDValue &N, SDValue &R, bool ShouldLookForGP);
bool SelectADDRri(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriS11_0(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriS11_1(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriS11_2(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectMEMriS11_2(SDValue& Addr, SDValue &Base, SDValue &Offset);
bool SelectADDRriS11_3(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset);
bool SelectADDRriU6_0(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
// Complex Pattern Selectors.
inline bool SelectAddrGA(SDValue &N, SDValue &R); inline bool SelectAddrGA(SDValue &N, SDValue &R);
inline bool SelectAddrGP(SDValue &N, SDValue &R); inline bool SelectAddrGP(SDValue &N, SDValue &R);
bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP); bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
Context not available.
return "Hexagon DAG->DAG Pattern Instruction Selection"; return "Hexagon DAG->DAG Pattern Instruction Selection";
} }
bool runOnMachineFunction(MachineFunction &MF) override { SDNode *SelectFrameIndex(SDNode *N);
Subtarget = &MF.getSubtarget<HexagonSubtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
}
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions. /// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op, bool SelectInlineAsmMemoryOperand(const SDValue &Op,
unsigned ConstraintID, unsigned ConstraintID,
std::vector<SDValue> &OutOps) override; std::vector<SDValue> &OutOps) override;
bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
SDNode *SelectLoad(SDNode *N); SDNode *SelectLoad(SDNode *N);
SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl); SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl); SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
Context not available.
SDNode *SelectConstantFP(SDNode *N); SDNode *SelectConstantFP(SDNode *N);
SDNode *SelectAdd(SDNode *N); SDNode *SelectAdd(SDNode *N);
// XformMskToBitPosU5Imm - Returns the bit position which // XformMskToBitPosU5Imm - Returns the bit position which
// the single bit 32 bit mask represents. // the single bit 32 bit mask represents.
// Used in Clr and Set bit immediate memops. // Used in Clr and Set bit immediate memops.
SDValue XformMskToBitPosU5Imm(uint32_t Imm) { SDValue XformMskToBitPosU5Imm(uint32_t Imm) {
int32_t bitPos; int32_t bitPos;
bitPos = Log2_32(Imm); bitPos = Log2_32(Imm);
assert(bitPos >= 0 && bitPos < 32 && assert(bitPos >= 0 && bitPos < 32 &&
"Constant out of range for 32 BitPos Memops"); "Constant out of range for 32 BitPos Memops");
return CurDAG->getTargetConstant(bitPos, MVT::i32); return CurDAG->getTargetConstant(bitPos, MVT::i32);
} }
// XformMskToBitPosU4Imm - Returns the bit position which the single bit 16 bit
// mask represents. Used in Clr and Set bit immediate memops.
SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
return XformMskToBitPosU5Imm(Imm);
}
// XformMskToBitPosU3Imm - Returns the bit position which the single bit 8 bit // XformMskToBitPosU4Imm - Returns the bit position which the single-bit
// mask represents. Used in Clr and Set bit immediate memops. // 16 bit mask represents. Used in Clr and Set bit immediate memops.
SDValue XformMskToBitPosU3Imm(uint8_t Imm) { SDValue XformMskToBitPosU4Imm(uint16_t Imm) {
return XformMskToBitPosU5Imm(Imm); return XformMskToBitPosU5Imm(Imm);
} }
// Return true if there is exactly one bit set in V, i.e., if V is one of the // XformMskToBitPosU3Imm - Returns the bit position which the single-bit
// following integers: 2^0, 2^1, ..., 2^31. // 8 bit mask represents. Used in Clr and Set bit immediate memops.
bool ImmIsSingleBit(uint32_t v) const { SDValue XformMskToBitPosU3Imm(uint8_t Imm) {
return isPowerOf2_32(v); return XformMskToBitPosU5Imm(Imm);
} }
// XformM5ToU5Imm - Return a target constant with the specified value, of type // Return true if there is exactly one bit set in V, i.e., if V is one of the
// i32 where the negative literal is transformed into a positive literal for // following integers: 2^0, 2^1, ..., 2^31.
// use in -= memops. bool ImmIsSingleBit(uint32_t v) const {
inline SDValue XformM5ToU5Imm(signed Imm) { return isPowerOf2_32(v);
assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops"); }
return CurDAG->getTargetConstant( - Imm, MVT::i32);
}
// XformM5ToU5Imm - Return a target constant with the specified value, of
// type i32 where the negative literal is transformed into a positive literal
// for use in -= memops.
inline SDValue XformM5ToU5Imm(signed Imm) {
assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
return CurDAG->getTargetConstant( - Imm, MVT::i32);
}
// XformU7ToU7M1Imm - Return a target constant decremented by 1, in range // XformU7ToU7M1Imm - Return a target constant decremented by 1, in range
// [1..128], used in cmpb.gtu instructions. // [1..128], used in cmpb.gtu instructions.
inline SDValue XformU7ToU7M1Imm(signed Imm) { inline SDValue XformU7ToU7M1Imm(signed Imm) {
assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op"); assert((Imm >= 1 && Imm <= 128) && "Constant out of range for cmpb op");
return CurDAG->getTargetConstant(Imm - 1, MVT::i8); return CurDAG->getTargetConstant(Imm - 1, MVT::i8);
} }
// XformS8ToS8M1Imm - Return a target constant decremented by 1. // XformS8ToS8M1Imm - Return a target constant decremented by 1.
inline SDValue XformSToSM1Imm(signed Imm) { inline SDValue XformSToSM1Imm(signed Imm) {
return CurDAG->getTargetConstant(Imm - 1, MVT::i32); return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
} }
// XformU8ToU8M1Imm - Return a target constant decremented by 1. // XformU8ToU8M1Imm - Return a target constant decremented by 1.
inline SDValue XformUToUM1Imm(unsigned Imm) { inline SDValue XformUToUM1Imm(unsigned Imm) {
assert((Imm >= 1) && "Cannot decrement unsigned int less than 1"); assert((Imm >= 1) && "Cannot decrement unsigned int less than 1");
return CurDAG->getTargetConstant(Imm - 1, MVT::i32); return CurDAG->getTargetConstant(Imm - 1, MVT::i32);
} }
// XformSToSM2Imm - Return a target constant decremented by 2. // XformSToSM2Imm - Return a target constant decremented by 2.
inline SDValue XformSToSM2Imm(unsigned Imm) { inline SDValue XformSToSM2Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm - 2, MVT::i32); return CurDAG->getTargetConstant(Imm - 2, MVT::i32);
} }
// XformSToSM3Imm - Return a target constant decremented by 3. // XformSToSM3Imm - Return a target constant decremented by 3.
inline SDValue XformSToSM3Imm(unsigned Imm) { inline SDValue XformSToSM3Imm(unsigned Imm) {
return CurDAG->getTargetConstant(Imm - 3, MVT::i32); return CurDAG->getTargetConstant(Imm - 3, MVT::i32);
} }
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "HexagonGenDAGISel.inc" #include "HexagonGenDAGISel.inc"
private: private:
bool isValueExtension(SDValue const &Val, unsigned FromBits, SDValue &Src); bool isValueExtension(const SDValue &Val, unsigned FromBits, SDValue &Src);
}; }; // end HexagonDAGToDAGISel
} // end anonymous namespace } // end anonymous namespace
/// createHexagonISelDag - This pass converts a legalized DAG into a /// createHexagonISelDag - This pass converts a legalized DAG into a
/// Hexagon-specific DAG, ready for instruction scheduling. /// Hexagon-specific DAG, ready for instruction scheduling.
/// ///
FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM, namespace llvm {
CodeGenOpt::Level OptLevel) { FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
CodeGenOpt::Level OptLevel) {
return new HexagonDAGToDAGISel(TM, OptLevel); return new HexagonDAGToDAGISel(TM, OptLevel);
} }
}
static void initializePassOnce(PassRegistry &Registry) { static void initializePassOnce(PassRegistry &Registry) {
const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection"; const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
Context not available.
} }
static bool IsS11_0_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
// immS16 predicate - True if the immediate fits in a 16-bit sign extended
// field.
int64_t v = (int64_t)N->getSExtValue();
return isInt<11>(v);
}
static bool IsS11_1_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
// immS16 predicate - True if the immediate fits in a 16-bit sign extended
// field.
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<11,1>(v);
}
static bool IsS11_2_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
// immS16 predicate - True if the immediate fits in a 16-bit sign extended
// field.
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<11,2>(v);
}
static bool IsS11_3_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
// immS16 predicate - True if the immediate fits in a 16-bit sign extended
// field.
int64_t v = (int64_t)N->getSExtValue();
return isShiftedInt<11,3>(v);
}
static bool IsU6_0_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
// u6 predicate - True if the immediate fits in a 6-bit unsigned extended
// field.
int64_t v = (int64_t)N->getSExtValue();
return isUInt<6>(v);
}
static bool IsU6_1_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
// u6 predicate - True if the immediate fits in a 6-bit unsigned extended
// field.
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<6,1>(v);
}
static bool IsU6_2_Offset(SDNode * S) {
ConstantSDNode *N = cast<ConstantSDNode>(S);
// u6 predicate - True if the immediate fits in a 6-bit unsigned extended
// field.
int64_t v = (int64_t)N->getSExtValue();
return isShiftedUInt<6,2>(v);
}
// Intrinsics that return a a predicate. // Intrinsics that return a a predicate.
static unsigned doesIntrinsicReturnPredicate(unsigned ID) static unsigned doesIntrinsicReturnPredicate(unsigned ID)
{ {
Context not available.
} }
} }
SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD, SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
unsigned Opcode, unsigned Opcode,
SDLoc dl) SDLoc dl) {
{
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
EVT LoadedVT = LD->getMemoryVT(); EVT LoadedVT = LD->getMemoryVT();
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
SDValue Offset = LD->getOffset(); SDValue Offset = LD->getOffset();
SDNode *OffsetNode = Offset.getNode(); SDNode *OffsetNode = Offset.getNode();
int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue(); int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
SDValue N1 = LD->getOperand(1);
SDValue CPTmpN1_0; const HexagonInstrInfo &TII = *HST.getInstrInfo();
SDValue CPTmpN1_1; if (TII.isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) && SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
N1.getNode()->getValueType(0) == MVT::i32) { MVT::Other, Base, TargetConst,
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
if (TII->isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
MVT::Other, Base, TargetConst,
Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
SDValue(Result_1, 0));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = LD->getMemOperand();
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
const SDValue Froms[] = { SDValue(LD, 0),
SDValue(LD, 1),
SDValue(LD, 2)
};
const SDValue Tos[] = { SDValue(Result_2, 0),
SDValue(Result_1, 1),
SDValue(Result_1, 2)
};
ReplaceUses(Froms, Tos, 3);
return Result_2;
}
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::Other, Base, TargetConst0,
Chain); Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
MVT::i64, SDValue(Result_1, 0)); SDValue(Result_1, 0));
SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl,
MVT::i32, Base, TargetConstVal,
SDValue(Result_1, 1));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = LD->getMemOperand(); MemOp[0] = LD->getMemOperand();
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
const SDValue Froms[] = { SDValue(LD, 0), const SDValue Froms[] = { SDValue(LD, 0),
SDValue(LD, 1), SDValue(LD, 1),
SDValue(LD, 2) SDValue(LD, 2) };
};
const SDValue Tos[] = { SDValue(Result_2, 0), const SDValue Tos[] = { SDValue(Result_2, 0),
SDValue(Result_3, 0), SDValue(Result_1, 1),
SDValue(Result_1, 1) SDValue(Result_1, 2) };
};
ReplaceUses(Froms, Tos, 3); ReplaceUses(Froms, Tos, 3);
return Result_2; return Result_2;
} }
return SelectCode(LD);
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
Base, TargetConst0, Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_sxtw, dl, MVT::i64,
SDValue(Result_1, 0));
SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base, TargetConstVal,
SDValue(Result_1, 1));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = LD->getMemOperand();
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
const SDValue Froms[] = { SDValue(LD, 0),
SDValue(LD, 1),
SDValue(LD, 2) };
const SDValue Tos[] = { SDValue(Result_2, 0),
SDValue(Result_3, 0),
SDValue(Result_1, 1) };
ReplaceUses(Froms, Tos, 3);
return Result_2;
} }
SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD, SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
unsigned Opcode, unsigned Opcode,
SDLoc dl) SDLoc dl) {
{
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
EVT LoadedVT = LD->getMemoryVT(); EVT LoadedVT = LD->getMemoryVT();
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
SDValue Offset = LD->getOffset(); SDValue Offset = LD->getOffset();
SDNode *OffsetNode = Offset.getNode(); SDNode *OffsetNode = Offset.getNode();
int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue(); int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
SDValue N1 = LD->getOperand(1);
SDValue CPTmpN1_0;
SDValue CPTmpN1_1;
if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
N1.getNode()->getValueType(0) == MVT::i32) {
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
if (TII->isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::i32, MVT::Other, Base,
TargetConstVal, Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32,
TargetConst0);
SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
MVT::i64, MVT::Other,
SDValue(Result_2,0),
SDValue(Result_1,0));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = LD->getMemOperand();
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
const SDValue Froms[] = { SDValue(LD, 0),
SDValue(LD, 1),
SDValue(LD, 2)
};
const SDValue Tos[] = { SDValue(Result_3, 0),
SDValue(Result_1, 1),
SDValue(Result_1, 2)
};
ReplaceUses(Froms, Tos, 3);
return Result_3;
}
// Generate an indirect load. const HexagonInstrInfo &TII = *HST.getInstrInfo();
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); if (TII.isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::Other, MVT::i32, MVT::Other, Base,
Base, TargetConst0, Chain); TargetConstVal, Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A2_tfrsi, dl, MVT::i32, SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
TargetConst0);
SDNode *Result_3 = CurDAG->getMachineNode(Hexagon::A2_combinew, dl,
MVT::i64, MVT::Other, MVT::i64, MVT::Other,
SDValue(Result_2,0), TargetConst0,
SDValue(Result_1,0)); SDValue(Result_1,0));
// Add offset to base.
SDNode* Result_4 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base, TargetConstVal,
SDValue(Result_1, 1));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = LD->getMemOperand(); MemOp[0] = LD->getMemOperand();
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
const SDValue Froms[] = { SDValue(LD, 0), const SDValue Froms[] = { SDValue(LD, 0),
SDValue(LD, 1), SDValue(LD, 1),
SDValue(LD, 2) SDValue(LD, 2) };
}; const SDValue Tos[] = { SDValue(Result_2, 0),
const SDValue Tos[] = { SDValue(Result_3, 0), // Load value. SDValue(Result_1, 1),
SDValue(Result_4, 0), // New address. SDValue(Result_1, 2) };
SDValue(Result_1, 1)
};
ReplaceUses(Froms, Tos, 3); ReplaceUses(Froms, Tos, 3);
return Result_3; return Result_2;
} }
return SelectCode(LD); // Generate an indirect load.
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::Other, Base, TargetConst0,
Chain);
SDNode *Result_2 = CurDAG->getMachineNode(Hexagon::A4_combineir, dl,
MVT::i64, MVT::Other,
TargetConst0,
SDValue(Result_1,0));
// Add offset to base.
SDNode* Result_3 = CurDAG->getMachineNode(Hexagon::A2_addi, dl, MVT::i32,
Base, TargetConstVal,
SDValue(Result_1, 1));
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = LD->getMemOperand();
cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1);
const SDValue Froms[] = { SDValue(LD, 0),
SDValue(LD, 1),
SDValue(LD, 2) };
const SDValue Tos[] = { SDValue(Result_2, 0), // Load value.
SDValue(Result_3, 0), // New address.
SDValue(Result_1, 1) };
ReplaceUses(Froms, Tos, 3);
return Result_2;
} }
Context not available.
EVT LoadedVT = LD->getMemoryVT(); EVT LoadedVT = LD->getMemoryVT();
unsigned Opcode = 0; unsigned Opcode = 0;
// Check for zero ext loads. // Check for zero extended loads. Treat any-extend loads as zero extended
bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD); // loads.
ISD::LoadExtType ExtType = LD->getExtensionType();
bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
// Figure out the opcode. // Figure out the opcode.
const HexagonInstrInfo *TII = Subtarget->getInstrInfo(); const HexagonInstrInfo &TII = *HST.getInstrInfo();
if (LoadedVT == MVT::i64) { if (LoadedVT == MVT::i64) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII.isValidAutoIncImm(LoadedVT, Val))
Opcode = Hexagon::L2_loadrd_pi; Opcode = Hexagon::L2_loadrd_pi;
else else
Opcode = Hexagon::L2_loadrd_io; Opcode = Hexagon::L2_loadrd_io;
} else if (LoadedVT == MVT::i32) { } else if (LoadedVT == MVT::i32) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII.isValidAutoIncImm(LoadedVT, Val))
Opcode = Hexagon::L2_loadri_pi; Opcode = Hexagon::L2_loadri_pi;
else else
Opcode = Hexagon::L2_loadri_io; Opcode = Hexagon::L2_loadri_io;
} else if (LoadedVT == MVT::i16) { } else if (LoadedVT == MVT::i16) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII.isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi; Opcode = IsZeroExt ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadrh_pi;
else else
Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io; Opcode = IsZeroExt ? Hexagon::L2_loadruh_io : Hexagon::L2_loadrh_io;
} else if (LoadedVT == MVT::i8) { } else if (LoadedVT == MVT::i8) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII.isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi; Opcode = IsZeroExt ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrb_pi;
else else
Opcode = zextval ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io; Opcode = IsZeroExt ? Hexagon::L2_loadrub_io : Hexagon::L2_loadrb_io;
} else } else
llvm_unreachable("unknown memory type"); llvm_unreachable("unknown memory type");
// For zero ext i64 loads, we need to add combine instructions. // For zero extended i64 loads, we need to add combine instructions.
if (LD->getValueType(0) == MVT::i64 && if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
LD->getExtensionType() == ISD::ZEXTLOAD) {
return SelectIndexedLoadZeroExtend64(LD, Opcode, dl); return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
} // Handle sign extended i64 loads.
if (LD->getValueType(0) == MVT::i64 && if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
LD->getExtensionType() == ISD::SEXTLOAD) {
// Handle sign ext i64 loads.
return SelectIndexedLoadSignExtend64(LD, Opcode, dl); return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
}
if (TII->isValidAutoIncImm(LoadedVT, Val)) { if (TII.isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32); SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode* Result = CurDAG->getMachineNode(Opcode, dl, SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
LD->getValueType(0), LD->getValueType(0),
Context not available.
// Get the constant value. // Get the constant value.
int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue(); int32_t Val = cast<ConstantSDNode>(OffsetNode)->getSExtValue();
EVT StoredVT = ST->getMemoryVT(); EVT StoredVT = ST->getMemoryVT();
EVT ValueVT = Value.getValueType();
// Offset value must be within representable range // Offset value must be within representable range
// and must have correct alignment properties. // and must have correct alignment properties.
const HexagonInstrInfo *TII = Subtarget->getInstrInfo(); const HexagonInstrInfo &TII = *HST.getInstrInfo();
if (TII->isValidAutoIncImm(StoredVT, Val)) { if (TII.isValidAutoIncImm(StoredVT, Val)) {
SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
Chain};
unsigned Opcode = 0; unsigned Opcode = 0;
// Figure out the post inc version of opcode. // Figure out the post inc version of opcode.
Context not available.
else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi; else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
else llvm_unreachable("unknown memory type"); else llvm_unreachable("unknown memory type");
if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg,
dl, MVT::i32, Value);
}
SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
Chain};
// Build post increment store. // Build post increment store.
SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32, SDNode* Result = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
MVT::Other, Ops); MVT::Other, Ops);
Context not available.
} }
// Note: Order of operands matches the def of instruction: // Note: Order of operands matches the def of instruction:
// def STrid : STInst<(outs), (ins MEMri:$addr, DoubleRegs:$src1), ... // def S2_storerd_io
// : STInst<(outs), (ins IntRegs:$base, imm:$offset, DoubleRegs:$src1), ...
// and it differs for POST_ST* for instance. // and it differs for POST_ST* for instance.
SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value, SDValue Ops[] = { Base, CurDAG->getTargetConstant(0, MVT::i32), Value,
Chain}; Chain};
Context not available.
return Result_2; return Result_2;
} }
SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) { SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
SDLoc dl(N); SDLoc dl(N);
StoreSDNode *ST = cast<StoreSDNode>(N); StoreSDNode *ST = cast<StoreSDNode>(N);
Context not available.
return SelectCode(N); return SelectCode(N);
} }
// //
// Map predicate true (encoded as -1 in LLVM) to a XOR. // Map predicate true (encoded as -1 in LLVM) to a XOR.
// //
Context not available.
return Result; return Result;
} }
SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
int FX = cast<FrameIndexSDNode>(N)->getIndex();
SDValue FI = CurDAG->getTargetFrameIndex(FX, MVT::i32);
SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
SDLoc DL(N);
SDNode *R = CurDAG->getMachineNode(Hexagon::TFR_FI, DL, MVT::i32, FI, Zero);
if (N->getHasDebugValue())
CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
return R;
}
SDNode *HexagonDAGToDAGISel::Select(SDNode *N) { SDNode *HexagonDAGToDAGISel::Select(SDNode *N) {
if (N->isMachineOpcode()) { if (N->isMachineOpcode()) {
Context not available.
return nullptr; // Already selected. return nullptr; // Already selected.
} }
switch (N->getOpcode()) { switch (N->getOpcode()) {
case ISD::Constant: case ISD::Constant:
return SelectConstant(N); return SelectConstant(N);
Context not available.
case ISD::ConstantFP: case ISD::ConstantFP:
return SelectConstantFP(N); return SelectConstantFP(N);
case ISD::FrameIndex:
return SelectFrameIndex(N);
case ISD::ADD: case ISD::ADD:
return SelectAdd(N); return SelectAdd(N);
Context not available.
} }
//
// Hexagon_TODO: Five functions for ADDRri?! Surely there must be a better way
// to define these instructions.
//
bool HexagonDAGToDAGISel::SelectADDRri(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
bool HexagonDAGToDAGISel::SelectADDRriS11_0(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_0_Offset(Offset.getNode()));
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_0_Offset(Offset.getNode()));
}
bool HexagonDAGToDAGISel::SelectADDRriS11_1(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_1_Offset(Offset.getNode()));
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_1_Offset(Offset.getNode()));
}
bool HexagonDAGToDAGISel::SelectADDRriS11_2(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_2_Offset(Offset.getNode()));
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_2_Offset(Offset.getNode()));
}
bool HexagonDAGToDAGISel::SelectADDRriU6_0(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsU6_0_Offset(Offset.getNode()));
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsU6_0_Offset(Offset.getNode()));
}
bool HexagonDAGToDAGISel::SelectADDRriU6_1(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsU6_1_Offset(Offset.getNode()));
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsU6_1_Offset(Offset.getNode()));
}
bool HexagonDAGToDAGISel::SelectADDRriU6_2(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsU6_2_Offset(Offset.getNode()));
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsU6_2_Offset(Offset.getNode()));
}
bool HexagonDAGToDAGISel::SelectMEMriS11_2(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() != ISD::ADD) {
return(SelectADDRriS11_2(Addr, Base, Offset));
}
return SelectADDRriS11_2(Addr, Base, Offset);
}
bool HexagonDAGToDAGISel::SelectADDRriS11_3(SDValue& Addr, SDValue &Base,
SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_3_Offset(Offset.getNode()));
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return (IsS11_3_Offset(Offset.getNode()));
}
bool HexagonDAGToDAGISel::SelectADDRrr(SDValue &Addr, SDValue &R1,
SDValue &R2) {
if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
if (isInt<13>(CN->getSExtValue()))
return false; // Let the reg+imm pattern catch this!
R1 = Addr.getOperand(0);
R2 = Addr.getOperand(1);
return true;
}
R1 = Addr;
return true;
}
// Handle generic address case. It is accessed from inlined asm =m constraints,
// which could have any kind of pointer.
bool HexagonDAGToDAGISel::SelectAddr(SDNode *Op, SDValue Addr,
SDValue &Base, SDValue &Offset) {
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // Direct calls.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::ADD) {
Base = Addr.getOperand(0);
Offset = Addr.getOperand(1);
return true;
}
Base = Addr;
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
bool HexagonDAGToDAGISel:: bool HexagonDAGToDAGISel::
SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
std::vector<SDValue> &OutOps) { std::vector<SDValue> &OutOps) {
SDValue Op0, Op1; SDValue Inp = Op, Res;
switch (ConstraintID) { switch (ConstraintID) {
case InlineAsm::Constraint_o: // Offsetable. case InlineAsm::Constraint_o: // Offsetable.
case InlineAsm::Constraint_v: // Not offsetable. case InlineAsm::Constraint_v: // Not offsetable.
default: return true; default:
return true;
case InlineAsm::Constraint_m: // Memory. case InlineAsm::Constraint_m: // Memory.
if (!SelectAddr(Op.getNode(), Op, Op0, Op1)) if (SelectAddrFI(Inp, Res))
return true; OutOps.push_back(Res);
else
OutOps.push_back(Inp);
break; break;
} }
OutOps.push_back(Op0); OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
OutOps.push_back(Op1);
return false;
}
//===--------------------------------------------------------------------===//
// Return true if the non-GP-relative global address can be folded.
//===--------------------------------------------------------------------===//
inline bool HexagonDAGToDAGISel::foldGlobalAddress(SDValue &N, SDValue &R) {
return foldGlobalAddressImpl(N, R, false);
}
//===--------------------------------------------------------------------===//
// Return true if the GP-relative global address can be folded.
//===--------------------------------------------------------------------===//
inline bool HexagonDAGToDAGISel::foldGlobalAddressGP(SDValue &N, SDValue &R) {
return foldGlobalAddressImpl(N, R, true);
}
//===--------------------------------------------------------------------===//
// Fold offset of the global address if number of uses are below threshold.
//===--------------------------------------------------------------------===//
bool HexagonDAGToDAGISel::foldGlobalAddressImpl(SDValue &N, SDValue &R,
bool ShouldLookForGP) {
if (N.getOpcode() == ISD::ADD) {
SDValue N0 = N.getOperand(0);
SDValue N1 = N.getOperand(1);
if ((ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32_GP)) ||
(!ShouldLookForGP && (N0.getOpcode() == HexagonISD::CONST32))) {
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1);
GlobalAddressSDNode *GA =
dyn_cast<GlobalAddressSDNode>(N0.getOperand(0));
if (Const && GA &&
(GA->getOpcode() == ISD::TargetGlobalAddress)) {
if (N0.getOpcode() == HexagonISD::CONST32)
return false;
R = CurDAG->getTargetGlobalAddress(GA->getGlobal(),
SDLoc(Const),
N.getValueType(),
GA->getOffset() +
(uint64_t)Const->getSExtValue());
return true;
}
}
}
return false; return false;
} }
Context not available.
return false; return false;
} }
bool HexagonDAGToDAGISel::isValueExtension(SDValue const &Val, bool HexagonDAGToDAGISel::isValueExtension(const SDValue &Val,
unsigned FromBits, SDValue &Src) { unsigned FromBits, SDValue &Src) {
unsigned Opc = Val.getOpcode(); unsigned Opc = Val.getOpcode();
switch (Opc) { switch (Opc) {
case ISD::SIGN_EXTEND: case ISD::SIGN_EXTEND:
Context not available.

lib/Target/Hexagon/HexagonISelLowering.cpp

Context not available.
// Turn FP extload into load/fextend. // Turn FP extload into load/fextend.
for (MVT VT : MVT::fp_valuetypes()) for (MVT VT : MVT::fp_valuetypes())
setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
// Hexagon has a i1 sign extending load.
for (MVT VT : MVT::integer_valuetypes()) // No extending loads from i32.
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand); for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
}
// Turn FP truncstore into trunc + store. // Turn FP truncstore into trunc + store.
setTruncStoreAction(MVT::f64, MVT::f32, Expand); setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Context not available.
setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
setOperationAction(ISD::MULHS, MVT::i64, Expand); setOperationAction(ISD::MULHS, MVT::i64, Expand);
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
Context not available.

lib/Target/Hexagon/HexagonInstrInfo.td

Context not available.
// Generate frameindex addresses. // Generate frameindex addresses.
let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
isPseudo = 1, isCodeGenOnly = 1 in isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in
def TFR_FI: ALU32_ri<(outs IntRegs:$Rd), (ins FrameIndex:$fi), def TFR_FI: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$fi, s32Imm:$Off), "">;
".error",
[(set (i32 IntRegs:$Rd), ADDRri:$fi)]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CRUSER - Type. // CRUSER - Type.
Context not available.
def: Pat<(i64 (sext (i1 PredRegs:$src1))), def: Pat<(i64 (sext (i1 PredRegs:$src1))),
(A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>; (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>;
// Convert sign-extended load back to load and sign extend.
// i32 -> i64
def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),
(i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;
// Zero extends. // Zero extends.
// i1 -> i32 // i1 -> i32
def: Pat<(i32 (zext (i1 PredRegs:$src1))), def: Pat<(i32 (zext (i1 PredRegs:$src1))),
Context not available.
def: Pat<(i64 (anyext (i1 PredRegs:$src1))), def: Pat<(i64 (anyext (i1 PredRegs:$src1))),
(A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>; (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>;
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),
(i32 32))),
(i64 (zextloadi32 ADDRriS11_2:$srcLow)))),
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),
(L2_loadri_io AddrFI:$srcLow, 0)))>;
// Multiply 64-bit unsigned and use upper result. // Multiply 64-bit unsigned and use upper result.
def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)), def : Pat <(mulhu (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
(A2_addp (A2_addp
Context not available.

lib/Target/Hexagon/HexagonInstrInfoV4.td

Context not available.
def: Pat<(i64 (zext (i32 IntRegs:$src1))), def: Pat<(i64 (zext (i32 IntRegs:$src1))),
(Zext64 IntRegs:$src1)>; (Zext64 IntRegs:$src1)>;
// zext i32->i64
def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),
(i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
let AddedComplexity = 100 in
def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s30_2ImmPred:$offset)))),
(i64 (A4_combineir 0, (L2_loadri_io IntRegs:$src1,
s30_2ImmPred:$offset)))>;
// anyext i32->i64
def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),
(i64 (A4_combineir 0, (L2_loadri_io AddrFI:$src1, 0)))>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// LD - // LD -
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
Context not available.

lib/Target/Hexagon/HexagonOperands.td

Context not available.
def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>; def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>;
def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>; def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>;
// Addressing modes.
def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
def ADDRriS11_0 : ComplexPattern<i32, 2, "SelectADDRriS11_0", [frameindex], []>;
def ADDRriS11_1 : ComplexPattern<i32, 2, "SelectADDRriS11_1", [frameindex], []>;
def ADDRriS11_2 : ComplexPattern<i32, 2, "SelectADDRriS11_2", [frameindex], []>;
def ADDRriS11_3 : ComplexPattern<i32, 2, "SelectADDRriS11_3", [frameindex], []>;
def ADDRriU6_0 : ComplexPattern<i32, 2, "SelectADDRriU6_0", [frameindex], []>;
def ADDRriU6_1 : ComplexPattern<i32, 2, "SelectADDRriU6_1", [frameindex], []>;
def ADDRriU6_2 : ComplexPattern<i32, 2, "SelectADDRriU6_2", [frameindex], []>;
// Address operands. // Address operands.
def MEMrr : Operand<i32> {
let PrintMethod = "printMEMrrOperand";
let MIOperandInfo = (ops IntRegs, IntRegs);
}
def MEMri : Operand<i32> {
let PrintMethod = "printMEMriOperand";
let MIOperandInfo = (ops IntRegs, IntRegs);
}
def MEMri_s11_2 : Operand<i32>,
ComplexPattern<i32, 2, "SelectMEMriS11_2", []> {
let PrintMethod = "printMEMriOperand";
let MIOperandInfo = (ops IntRegs, s11Imm);
}
def FrameIndex : Operand<i32> {
let PrintMethod = "printFrameIndexOperand";
let MIOperandInfo = (ops IntRegs, s11Imm);
}
let PrintMethod = "printGlobalOperand" in { let PrintMethod = "printGlobalOperand" in {
def globaladdress : Operand<i32>; def globaladdress : Operand<i32>;
def globaladdressExt : Operand<i32>; def globaladdressExt : Operand<i32>;
Context not available.

lib/Target/Hexagon/HexagonRegisterInfo.cpp

Context not available.
Offset -= 2 * Hexagon_WordSize; Offset -= 2 * Hexagon_WordSize;
} }
const unsigned FrameSize = MFI.getStackSize(); unsigned FrameSize = MFI.getStackSize();
if (MI.getOpcode() == Hexagon::TFR_FI)
MI.setDesc(TII.get(Hexagon::A2_addi));
if (!MFI.hasVarSizedObjects() && if (!MFI.hasVarSizedObjects() &&
TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
Context not available.

test/CodeGen/Hexagon/union-1.ll

Context not available.
; CHECK: word ; CHECK: word
; CHECK-NOT: combine(#0 ; CHECK-NOT: combine(#0
; CHECK: jump bar ; CHECK: jump bar
; XFAIL: *
; Disable this test temporarily.
define void @word(i32* nocapture %a) nounwind { define void @word(i32* nocapture %a) nounwind {
entry: entry:
Context not available.