Do not use isel on P7 and P8

[ohsallen]

Summary

It appears that using branches is almost always better than using isel for P7 and P8, because of branch prediction — the decision outcome has to be almost completely random for isel to win. Also isel has a way higher latency for P8 than for A2, for instance. This patch disables the usage of isel for P7 and P8, and employs regular branches instead.

Had to change some regression tests to use A2 instead of P7 for checking that isel is generated. There are still 2 tests for which I have problems:

LLVM :: CodeGen/PowerPC/ifcvt.ll
LLVM :: CodeGen/PowerPC/p8-isel-sched.ll

ifcvt.ll: using A2 does not generate isel (Hal: seems fishy, right?)
p8-isel-sched.ll: shall we remove this testcase?

Thanks,
Olivier

[hfinkel]

ifcvt.ll: using A2 does not generate isel (Hal: seems fishy, right?)

Yea, we should figure this out.

p8-isel-sched.ll: shall we remove this testcase?

No, but once you control this using some target feature, you can enable it specifically for this test.

Also, one more wrinkle, we should still generate isel on the p7/p8 when optimizing for size.

lib/Target/PowerPC/PPCSubtarget.h

271

I don't want to do it this way. Either just remove HasISEL from the P7/P8 processor definitions, or add a ISELIsSlow (or whatever) to PPC.td, but we shouldn't hard code it like this here.

test/CodeGen/PowerPC/crbit-asm.ll

1

Please keep the isel test coverage here (and in crbit.ll below), but we can use different -check-prefix when running on the pwr7 vs. the a2.

[ohsallen]

Thanks for the comments, Hal. Here is a version with a change in the processor definitions of P7/P8. The logic has been moved into enableEarlyIfConversion(), and the optsize attribute is considered. I had to change the signature of that function for that purpose.

[echristo]

The target independent parts look fine to me.

-eric

[hfinkel]

I've not run benchmarks on the P8, only the P7 (I did 20 test suite runs in each configuration today), but I think that the situation is more complicated than you imply...

With this patch I see (negative is speedup):

External/SPEC/CFP2006/444.namd/444.namd
-29.3699% +/- 19.5658%
External/SPEC/CINT2006/483.xalancbmk/483.xalancbmk
2.46854% +/- 0.541648%
MultiSource/Benchmarks/McCat/04-bisect/bisect
15.5624% +/- 5.32078%
MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio
31.4063% +/- 19.7579%

So the namd speedup is nice, but essentially everything else is a slowdown. I think that we need a more in-depth analysis of what's going on here.

[ohsallen]

As discussed with Hal, using the isel instruction can be beneficial with the current infrastructure because it reduces the number of basic blocks, and enables some late optimizations. Ultimately, we should keep the select instructions and expand them into branches after those optimizations happened. In the meantime, we will keep using isel by default and provide a -misel/-mno-isel option in Clang.

Thanks,
Olivier

include/llvm/Target/TargetSubtargetInfo.h

public:
   /// a finer grain to tune the register allocator.
   virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
 
   /// \brief Enable use of alias analysis during code generation (during MI
   /// scheduling, DAGCombine, etc.).
   virtual bool useAA() const;
 
   /// \brief Enable the use of the early if conversion pass.
-  virtual bool enableEarlyIfConversion() const { return false; }
+  virtual bool enableEarlyIfConversion(const MachineFunction &MF) const { return false; }
 
   /// \brief Return PBQPConstraint(s) for the target.
   ///
   /// Override to provide custom PBQP constraints.
   virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
     return nullptr;
   }
 

lib/CodeGen/EarlyIfConversion.cpp

bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
   return Changed;
 }
 
 bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
   DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
                << "********** Function: " << MF.getName() << '\n');
   // Only run if conversion if the target wants it.
   const TargetSubtargetInfo &STI = MF.getSubtarget();
-  if (!STI.enableEarlyIfConversion())
+  if (!STI.enableEarlyIfConversion(MF))
     return false;
 
   TII = STI.getInstrInfo();
   TRI = STI.getRegisterInfo();
   SchedModel = STI.getSchedModel();
   MRI = &MF.getRegInfo();
   DomTree = &getAnalysis<MachineDominatorTree>();
   Loops = getAnalysisIfAvailable<MachineLoopInfo>();

lib/Target/AArch64/AArch64Subtarget.h

public:
   /// memset with zero passed as the second argument. Otherwise it
   /// returns null.
   const char *getBZeroEntry() const;
 
   void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
                            MachineInstr *end,
                            unsigned NumRegionInstrs) const override;
 
-  bool enableEarlyIfConversion() const override;
+  bool enableEarlyIfConversion(const MachineFunction &MF) const override;
 
   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
 };
 } // End llvm namespace
 
 #endif

lib/Target/AArch64/AArch64Subtarget.cpp

void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
                                          MachineInstr *begin, MachineInstr *end,
                                          unsigned NumRegionInstrs) const {
   // LNT run (at least on Cyclone) showed reasonably significant gains for
   // bi-directional scheduling. 253.perlbmk.
   Policy.OnlyTopDown = false;
   Policy.OnlyBottomUp = false;
 }
 
-bool AArch64Subtarget::enableEarlyIfConversion() const {
+bool AArch64Subtarget::enableEarlyIfConversion(const MachineFunction &MF) const {
   return EnableEarlyIfConvert;
 }
 
 std::unique_ptr<PBQPRAConstraint>
 AArch64Subtarget::getCustomPBQPConstraints() const {
   if (!isCortexA57())
     return nullptr;
 
   return llvm::make_unique<A57ChainingConstraint>();
 }
 
 const AArch64RegisterInfo *AArch64Subtarget::getRegisterInfo() const {
   return getTargetMachine().getRegisterInfo();
 }

lib/Target/PowerPC/PPC.td

 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
                                         "Enable the lfiwax instruction">;
 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
                                         "Enable the fri[mnpz] instructions">;
 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
                                         "Enable the isel instruction">;
+def FeatureSlowISEL  : SubtargetFeature<"slow-isel","HasSlowISEL", "true",
+                                       "Using isel is usually slower than using branches",
+                                       [FeatureISEL]>;
 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
                                         "Enable the popcnt[dw] instructions">;
 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
                                         "Enable the ldbrx instruction">;
 def FeatureCMPB      : SubtargetFeature<"cmpb", "HasCMPB", "true",
                                         "Enable the cmpb instruction">;
 def FeatureICBT      : SubtargetFeature<"icbt","HasICBT", "true",
                                         "Enable icbt instruction">;

     
 */
 def ProcessorFeatures {
     list<SubtargetFeature> Power8FeatureList =
         [DirectivePwr8, FeatureAltivec, FeatureP8Altivec, FeatureVSX, 
         FeatureP8Vector, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, 
         FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
         FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
-        FeatureFPRND, FeatureFPCVT, FeatureISEL,
+        FeatureFPRND, FeatureFPCVT, FeatureISEL, FeatureSlowISEL,
         FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX, FeatureP8Crypto,
         Feature64Bit /*, Feature64BitRegs */, FeatureICBT,
         FeaturePartwordAtomic, DeprecatedMFTB, DeprecatedDST];
 }
 
 def : ProcessorModel<"970", G5Model,
                   [Directive970, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt,
def : ProcessorModel<"pwr6x", G5Model,
                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
                    FeatureFPRND, Feature64Bit,
                    DeprecatedMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr7", P7Model,
                   [DirectivePwr7, FeatureAltivec, FeatureVSX,
                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
-                   FeatureFPRND, FeatureFPCVT, FeatureISEL,
+                   FeatureFPRND, FeatureFPCVT, FeatureISEL, FeatureSlowISEL,
                    FeaturePOPCNTD, FeatureCMPB, FeatureLDBRX,
                    Feature64Bit /*, Feature64BitRegs */, FeaturePartwordAtomic,
                    DeprecatedMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 def : ProcessorModel<"ppc64", G5Model,
                   [Directive64, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,

lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
   // To "insert" these instructions we actually have to insert their
   // control-flow patterns.
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction::iterator It = BB;
   ++It;
 
   MachineFunction *F = BB->getParent();
 
-  if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
-                              MI->getOpcode() == PPC::SELECT_CC_I8 ||
-                              MI->getOpcode() == PPC::SELECT_I4 ||
-                              MI->getOpcode() == PPC::SELECT_I8)) {
+  if (Subtarget.enableEarlyIfConversion(*F) &&
+      (MI->getOpcode() == PPC::SELECT_CC_I4 ||
     SmallVector<MachineOperand, 2> Cond;
     if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
         MI->getOpcode() == PPC::SELECT_CC_I8)
       Cond.push_back(MI->getOperand(4));
     else
       Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
     Cond.push_back(MI->getOperand(1));
 

lib/Target/PowerPC/PPCInstrInfo.cpp

PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
   return 2;
 }
 
 // Select analysis.
 bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
                 const SmallVectorImpl<MachineOperand> &Cond,
                 unsigned TrueReg, unsigned FalseReg,
                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
-  if (!Subtarget.hasISEL())
+  if (!Subtarget.enableEarlyIfConversion(*MBB.getParent()))
     return false;
 
   if (Cond.size() != 2)
     return false;
 
   // If this is really a bdnz-like condition, then it cannot be turned into a
   // select.
   if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)

lib/Target/PowerPC/PPCSubtarget.h

 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
 
 #include "PPCFrameLowering.h"
 #include "PPCISelLowering.h"
 #include "PPCInstrInfo.h"
 #include "PPCSelectionDAGInfo.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
+#include "llvm/IR/Function.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <string>
 
 #define GET_SUBTARGETINFO_HEADER
 #include "PPCGenSubtargetInfo.inc"
 
 // GCC #defines PPC on Linux but we use it as our namespace name
protected:
   bool HasFSQRT;
   bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
   bool HasRecipPrec;
   bool HasSTFIWX;
   bool HasLFIWAX;
   bool HasFPRND;
   bool HasFPCVT;
   bool HasISEL;
+  bool HasSlowISEL;
   bool HasPOPCNTD;
   bool HasCMPB;
   bool HasLDBRX;
   bool IsBookE;
   bool HasOnlyMSYNC;
   bool IsE500;
   bool IsPPC4xx;
   bool IsPPC6xx;
public:
   bool hasSPE() const { return HasSPE; }
   bool hasQPX() const { return HasQPX; }
   bool hasVSX() const { return HasVSX; }
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }
   bool hasMFOCRF() const { return HasMFOCRF; }
   bool hasISEL() const { return HasISEL; }
+  bool hasSlowISEL() const { return HasSlowISEL; }
   bool hasPOPCNTD() const { return HasPOPCNTD; }
   bool hasCMPB() const { return HasCMPB; }
   bool hasLDBRX() const { return HasLDBRX; }
   bool isBookE() const { return IsBookE; }
   bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
   bool isPPC4xx() const { return IsPPC4xx; }
   bool isPPC6xx() const { return IsPPC6xx; }
   bool isE500() const { return IsE500; }
public:
 
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
   bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
   bool isSVR4ABI() const { return !isDarwinABI(); }
   bool isELFv2ABI() const;
 
-  bool enableEarlyIfConversion() const override { return hasISEL(); }
+  // For some targets, using branches is almost always better than using
+  // select: the decision outcome needs to be almost completely random for isel
+  // to win, otherwise the branch predictor can predict the outcome. For such
+  // targets, only use select when optimizing for size.
+  bool enableEarlyIfConversion(const MachineFunction &MF) const override {
+    return hasISEL() &&
+           (!hasSlowISEL() ||
+            MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize));
+  }
 
   // Scheduling customization.
   bool enableMachineScheduler() const override;
   // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
   bool enablePostMachineScheduler() const override;
   AntiDepBreakMode getAntiDepBreakMode() const override;
   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
 

lib/Target/X86/X86Subtarget.h

public:
 
   /// This function returns true if the target has sincos() routine in its
   /// compiler runtime or math libraries.
   bool hasSinCos() const;
 
   /// Enable the MachineScheduler pass for all X86 subtargets.
   bool enableMachineScheduler() const override { return true; }
 
-  bool enableEarlyIfConversion() const override;
+  bool enableEarlyIfConversion(const MachineFunction &MF) const override;
 
   /// Return the instruction itineraries based on the subtarget selection.
   const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
 
   AntiDepBreakMode getAntiDepBreakMode() const override {
     return TargetSubtargetInfo::ANTIDEP_CRITICAL;
   }
 };
 
 } // End llvm namespace
 
 #endif

test/CodeGen/PowerPC/crbit-asm.ll

 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
 entry:
   %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
   %1 = and i8 %0, 1
   %tobool3 = icmp ne i8 %1, 0

 ; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1
 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
 ; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1
 ; CHECK-DAG: li [[REG4:[0-9]+]], 1
 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
 ; CHECK: blr
 }
 
-attributes #0 = { nounwind }
+attributes #0 = { nounwind optsize }
 

test/CodeGen/PowerPC/crbits.ll

 ; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
 ; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: crorc [[REG3:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG2]], [[REG3]]
 ; CHECK: blr
 }
 
-attributes #0 = { nounwind readnone }
+attributes #0 = { nounwind readnone optsize }
 

test/CodeGen/PowerPC/fold-zero.ll

 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck -check-prefix=CHECK-CRB %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-define i32 @test1(i1 %a, i32 %c) nounwind  {
+define i32 @test1(i1 %a, i32 %c) nounwind optsize  {
   %x = select i1 %a, i32 %c, i32 0
   ret i32 %x
 
 ; CHECK: @test1
 ; CHECK-NOT: li {{[0-9]+}}, 0
 ; CHECK: isel 3, 0,
 ; CHECK: blr
 }
 
-define i32 @test2(i1 %a, i32 %c) nounwind  {
+define i32 @test2(i1 %a, i32 %c) nounwind optsize {
   %x = select i1 %a, i32 0, i32 %c
   ret i32 %x
 
 ; CHECK-CRB: @test2
 ; CHECK-CRB-NOT: li {{[0-9]+}}, 0
 ; CHECK-CRB: isel 3, 0,
 ; CHECK-CRB: blr
 }
 

test/CodeGen/PowerPC/i1-ext-fold.ll

 
 ; CHECK-LABEL: @foo3
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 16
 ; CHECK: isel 3, 0, [[REG1]],
 ; CHECK: blr
 }
 
-attributes #0 = { nounwind readnone }
+attributes #0 = { nounwind readnone optsize }
 

test/CodeGen/PowerPC/i64-to-float.ll

 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-define float @foo(i64 %a) nounwind {
+define float @foo(i64 %a) nounwind optsize {
 entry:
   %x = sitofp i64 %a to float
   ret float %x
 
 ; CHECK: @foo
 ; CHECK: std 3,
 ; CHECK: lfd [[REG:[0-9]+]],
 ; CHECK: fcfids 1, [[REG]]
 ; CHECK: blr
 
 ; CHECK-VSX: @foo
 ; CHECK-VSX: std 3,
 ; CHECK-VSX: lxsdx [[REG:[0-9]+]],
 ; CHECK-VSX: fcfids 1, [[REG]]
 ; CHECK-VSX: blr
 }
 
-define double @goo(i64 %a) nounwind {
+define double @goo(i64 %a) nounwind optsize {
 entry:
   %x = sitofp i64 %a to double
   ret double %x
 
 ; CHECK: @goo
 ; CHECK: std 3,
 ; CHECK: lfd [[REG:[0-9]+]],
 ; CHECK: fcfid 1, [[REG]]
 ; CHECK: blr
 
 ; CHECK-VSX: @goo
 ; CHECK-VSX: std 3,
 ; CHECK-VSX: lxsdx [[REG:[0-9]+]],
 ; CHECK-VSX: xscvsxddp 1, [[REG]]
 ; CHECK-VSX: blr
 }
 
-define float @foou(i64 %a) nounwind {
+define float @foou(i64 %a) nounwind optsize {
 entry:
   %x = uitofp i64 %a to float
   ret float %x
 
 ; CHECK: @foou
 ; CHECK: std 3,
 ; CHECK: lfd [[REG:[0-9]+]],
 ; CHECK: fcfidus 1, [[REG]]
 ; CHECK: blr
 
 ; CHECK-VSX: @foou
 ; CHECK-VSX: std 3,
 ; CHECK-VSX: lxsdx [[REG:[0-9]+]],
 ; CHECK-VSX: fcfidus 1, [[REG]]
 ; CHECK-VSX: blr
 }
 
-define double @goou(i64 %a) nounwind {
+define double @goou(i64 %a) nounwind optsize {
 entry:
   %x = uitofp i64 %a to double
   ret double %x
 
 ; CHECK: @goou
 ; CHECK: std 3,
 ; CHECK: lfd [[REG:[0-9]+]],
 ; CHECK: fcfidu 1, [[REG]]

test/CodeGen/PowerPC/i64_fp_round.ll

 ; RUN: llc -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-define float @test(i64 %x) nounwind readnone {
+define float @test(i64 %x) nounwind readnone optsize {
 entry:
   %conv = sitofp i64 %x to float
   ret float %conv
 }
 
 ; Verify that we get the code sequence needed to avoid double-rounding.
 ; Note that only parts of the sequence are checked for here, to allow
 ; for minor code generation differences.

test/CodeGen/PowerPC/ifcvt.ll

 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
+define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) #0 {
 entry:
   %sext82 = shl i32 %d, 16
   %conv29 = ashr exact i32 %sext82, 16
   %cmp = icmp slt i32 %sext82, 0
   br i1 %cmp, label %cond.true, label %cond.false
 
 cond.true:                                        ; preds = %sw.epilog
   %and33 = and i32 %conv29, 32767
cond.end:                                         ; preds = %cond.false, %cond.true
   %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ]
   %sext83 = shl i32 %cond, 16
   %conv39 = ashr exact i32 %sext83, 16
   %add41 = sub i32 %b, %a
   %sub43 = add i32 %add41, %conv39
   ret i32 %sub43
 }
 
+attributes #0 = { optsize }

test/CodeGen/PowerPC/isel.ll

 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 ; RUN: llc -mcpu=a2 < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
 
-define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) {
+define i64 @test1(i64 %a, i64 %b, i64 %c, i64 %d) #0 {
 entry:
   %p = icmp uge i64 %a, %b
   %x = select i1 %p, i64 %c, i64 %d
   ret i64 %x
 ; CHECK: @test1
 ; CHECK: isel
 }
 
-define i32 @test2(i32 %a, i32 %b, i32 %c, i32 %d) {
+define i32 @test2(i32 %a, i32 %b, i32 %c, i32 %d) #0 {
 entry:
   %p = icmp uge i32 %a, %b
   %x = select i1 %p, i32 %c, i32 %d
   ret i32 %x
 ; CHECK: @test2
 ; CHECK: isel
 }
 
+attributes #0 = { optsize }

test/CodeGen/PowerPC/no-isel.ll

+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-ibm-linux-gnu"
+
+define signext i32 @i64cmp(i8* nocapture readonly %a, i8* nocapture readonly %b) {
+entry:
+  %0 = bitcast i8* %a to i64*
+  %1 = load i64, i64* %0, align 8
+  %2 = bitcast i8* %b to i64*
+  %3 = load i64, i64* %2, align 8
+  %cmp = icmp slt i64 %1, %3
+  %cmp1 = icmp sgt i64 %1, %3
+  %. = zext i1 %cmp1 to i32
+  %retval.0 = select i1 %cmp, i32 -1, i32 %.
+  ret i32 %retval.0
+; CHECK-NOT: isel
+}

test/CodeGen/PowerPC/p8-isel-sched.ll

 ; Make sure that we don't schedule all of the isels together, they should be
 ; intermixed with the adds because each isel starts a new dispatch group.
 ; CHECK-LABEL: @foo
 ; CHECK: isel
 ; CHECK: addi
 ; CHECK: isel
 ; CHECK: blr
 
-attributes #0 = { nounwind }
+attributes #0 = { nounwind optsize }
 

test/CodeGen/PowerPC/subreg-postra-2.ll

 
 if.then420:                                       ; preds = %while.end418
   unreachable
 
 if.end421:                                        ; preds = %while.end418
   unreachable
 }
 
-attributes #0 = { nounwind }
+attributes #0 = { nounwind optsize }
 

test/CodeGen/PowerPC/subreg-postra.ll

 if.end421:                                        ; preds = %if.then420, %while.end418
   unreachable
 }
 
 declare void @jbd2_journal_abort(i32*, i32 signext)
 
 declare void @__brelse(i32*)
 
-attributes #0 = { nounwind }
-attributes #1 = { nounwind }
+attributes #0 = { nounwind optsize }
+attributes #1 = { nounwind optsize }