Add the P8 VSX logical instructions

[nemanjai]

Summary

This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.

[hfinkel]

Fixing the triple issue below, this LGTM.

lib/Target/PowerPC/PPCInstrVSX.td

944

I assume the issue is with vnot_ppc (because the and/or/xor will still be promoted to v4i32).

test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll

5

Shouldn't this triple be powerpc64le-...?

[nemanjai]

I fixed the mismatch between the -march and -mtriple. Thanks for pointing it out Hal.

[kbarton]

Committed in Nemanja's behalf.
Committed revision 229694.

lib/Target/PowerPC/PPCInstrAltivec.td

 def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB),
                         "vpopcntw $vD, $vB", IIC_VecGeneral,
                         [(set v4i32:$vD, (ctpop v4i32:$vB))]>;
 def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB),
                         "vpopcntd $vD, $vB", IIC_VecGeneral,
                         [(set v2i64:$vD, (ctpop v2i64:$vB))]>;
 
 let isCommutable = 1 in {
-let AddedComplexity = 500 in {
 // FIXME: Use AddedComplexity > 400 to ensure these patterns match before the 
 //        VSX equivalents. We need to fix this up at some point. Two possible
 //        solutions for this problem:
 //        1. Disable Altivec patterns that compete with VSX patterns using the
 //           !HasVSX predicate. This essentially favours VSX over Altivec, in 
 //           hopes of reducing register pressure (larger register set using VSX 
 //           instructions than VMX instructions)
 //        2. Employ a more disciplined use of AddedComplexity, which would provide
 //           more fine-grained control than option 1. This would be beneficial
 //           if we find situations where Altivec is really preferred over VSX. 
 def VEQV  : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                      "veqv $vD, $vA, $vB", IIC_VecGeneral,
                      [(set v4i32:$vD, (vnot_ppc (xor v4i32:$vA, v4i32:$vB)))]>;
 def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                      "vnand $vD, $vA, $vB", IIC_VecGeneral,
                      [(set v4i32:$vD, (vnot_ppc (and v4i32:$vA, v4i32:$vB)))]>;
 def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                       "vorc $vD, $vA, $vB", IIC_VecGeneral,
                       [(set v4i32:$vD, (or v4i32:$vA,
                                            (vnot_ppc v4i32:$vB)))]>;
-} // AddedComplexity = 500
 } // isCommutable
 } // end HasP8Altivec

lib/Target/PowerPC/PPCInstrVSX.td

 def : Pat<(int_ppc_vsx_xvdivsp v4f32:$A, v4f32:$B),
           (XVDIVSP $A, $B)>;
 def : Pat<(int_ppc_vsx_xvdivdp v2f64:$A, v2f64:$B),
           (XVDIVDP $A, $B)>;
 
 } // AddedComplexity
 } // HasVSX
 
+// The following VSX instructions were introduced in Power ISA 2.07
+/* FIXME: if the operands are v2i64, these patterns will not match.
+   we should define new patterns or otherwise match the same patterns
+   when the elements are larger than i32.
+*/
+def HasP8Vector : Predicate<"PPCSubTarget->hasP8Vector()">;
+let Predicates = [HasP8Vector] in {
+let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
+let isCommutable = 1 in {
+  def XXLEQV : XX3Form<60, 186,
+                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                       "xxleqv $XT, $XA, $XB", IIC_VecGeneral,
+                       [(set v4i32:$XT, (vnot_ppc (xor v4i32:$XA, v4i32:$XB)))]>;
+  def XXLNAND : XX3Form<60, 178,
+                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                        "xxlnand $XT, $XA, $XB", IIC_VecGeneral,
+                        [(set v4i32:$XT, (vnot_ppc (and v4i32:$XA,
+                                                    v4i32:$XB)))]>;
+  } // isCommutable
+def XXLORC : XX3Form<60, 170,
+                     (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                     "xxlorc $XT, $XA, $XB", IIC_VecGeneral,
+                     [(set v4i32:$XT, (or v4i32:$XA, (vnot_ppc v4i32:$XB)))]>;
+} // AddedComplexity = 500
+} // HasP8Vector

test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll

 ; Check the miscellaneous logical vector operations added in P8
 ; 
-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
 ; Test x eqv y
 define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind {
        %tmp = xor <4 x i32> %x, %y
        %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
        ret <4 x i32> %ret_val
 ; CHECK: veqv 2, 2, 3
 }

test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll

+; Check the miscellaneous logical vector operations added in P8
+; 
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; Test x eqv y
+define <4 x i32> @test_xxleqv(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: xxleqv 34, 34, 35
+}
+
+; Test x xxlnand y
+define <4 x i32> @test_xxlnand(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = and <4 x i32> %x, %y
+       %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1>
+       ret <4 x i32> %ret_val
+; CHECK: xxlnand 34, 34, 35
+}
+
+; Test x xxlorc y
+define <4 x i32> @test_xxlorc(<4 x i32> %x, <4 x i32> %y) nounwind {
+       %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
+       %ret_val = or <4 x i32> %x, %tmp
+       ret <4 x i32> %ret_val
+; CHECK: xxlorc 34, 34, 35
+}
+
+; Test x eqv y
+define <8 x i16> @test_xxleqvv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+       %tmp = xor <8 x i16> %x, %y
+       %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+       ret <8 x i16> %ret_val
+; CHECK: xxleqv 34, 34, 35
+}
+
+; Test x xxlnand y
+define <8 x i16> @test_xxlnandv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+       %tmp = and <8 x i16> %x, %y
+       %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+       ret <8 x i16> %ret_val
+; CHECK: xxlnand 34, 34, 35
+}
+
+; Test x xxlorc y
+define <8 x i16> @test_xxlorcv8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
+       %tmp = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
+       %ret_val = or <8 x i16> %x, %tmp
+       ret <8 x i16> %ret_val
+; CHECK: xxlorc 34, 34, 35
+}
+

test/MC/Disassembler/PowerPC/vsx.txt

 0xf3 0x00 0xdb 0xa8
 
 # CHECK: xvtsqrtsp 6, 27
 0xf3 0x00 0xda 0xa8
 
 # CHECK: xxland 7, 63, 27
 0xf0 0xff 0xdc 0x14
 
+# CHECK: xxleqv 7, 63, 27
+0xf0 0xff 0xdd 0xd4
+
+# CHECK: xxlnand 7, 63, 27
+0xf0 0xff 0xdd 0x94
+
+# CHECK: xxlorc 7, 63, 27
+0xf0 0xff 0xdd 0x54
+
 # CHECK: xxlandc 7, 63, 27
 0xf0 0xff 0xdc 0x54
 
 # CHECK: xxlnor 7, 63, 27
 0xf0 0xff 0xdd 0x14
 
 # CHECK: xxlor 7, 63, 27
 0xf0 0xff 0xdc 0x94

test/MC/PowerPC/vsx.s

 # CHECK-LE: xvtsqrtdp 6, 27                    # encoding: [0xa8,0xdb,0x00,0xf3]
             xvtsqrtdp 6, 27
 # CHECK-BE: xvtsqrtsp 6, 27                    # encoding: [0xf3,0x00,0xda,0xa8]
 # CHECK-LE: xvtsqrtsp 6, 27                    # encoding: [0xa8,0xda,0x00,0xf3]
             xvtsqrtsp 6, 27
 # CHECK-BE: xxland 7, 63, 27                   # encoding: [0xf0,0xff,0xdc,0x14]
 # CHECK-LE: xxland 7, 63, 27                   # encoding: [0x14,0xdc,0xff,0xf0]
             xxland 7, 63, 27
+# CHECK-BE: xxleqv 7, 63, 27                   # encoding: [0xf0,0xff,0xdd,0xd4]
+# CHECK-LE: xxleqv 7, 63, 27                   # encoding: [0xd4,0xdd,0xff,0xf0]
+            xxleqv 7, 63, 27
+# CHECK-BE: xxlnand 7, 63, 27                  # encoding: [0xf0,0xff,0xdd,0x94]
+# CHECK-LE: xxlnand 7, 63, 27                  # encoding: [0x94,0xdd,0xff,0xf0]
+            xxlnand 7, 63, 27
+# CHECK-BE: xxlorc 7, 63, 27                   # encoding: [0xf0,0xff,0xdd,0x54]
+# CHECK-LE: xxlorc 7, 63, 27                   # encoding: [0x54,0xdd,0xff,0xf0]
+            xxlorc 7, 63, 27
 # CHECK-BE: xxlandc 7, 63, 27                  # encoding: [0xf0,0xff,0xdc,0x54]
 # CHECK-LE: xxlandc 7, 63, 27                  # encoding: [0x54,0xdc,0xff,0xf0]
             xxlandc 7, 63, 27
 # CHECK-BE: xxlnor 7, 63, 27                   # encoding: [0xf0,0xff,0xdd,0x14]
 # CHECK-LE: xxlnor 7, 63, 27                   # encoding: [0x14,0xdd,0xff,0xf0]
             xxlnor 7, 63, 27
 # CHECK-BE: xxlor 7, 63, 27                    # encoding: [0xf0,0xff,0xdc,0x94]
 # CHECK-LE: xxlor 7, 63, 27                    # encoding: [0x94,0xdc,0xff,0xf0]