X86TargetLowering::LowerToBT

[CSears]

Summary

This is a patch to X86TargetLowering::LowerToBT() which was hashed over on the Developers list with Intel concurring. I'm finally figuring out Phabricator and I expect a few more problems there.

bt_pat generates the BT instruction for X86 bit testing in cases where code size is important. It checks whether the -Oz (optimize for size) flag is set or whether the containing function's PGO cold attribute is set. If either are true it emits BT for tests of bits 8-31 instead of TEST. Previously, TEST was always used for bits 0-31 and BT was always used for bits 32-63.

Since the BT instruction is 16b smaller than TEST for the bits 8-31 case, 32b vs 48b, and not irredeemably slower, it makes sense to use BT in cases where size matters.

Similar logic is possible for BTC and BTS. However, LowerToBTC and LowerToBTS would need to be written and used and that's a larger patch.

[mehdi_amini]

We need the non regression test to be a .ll with the appropriate "CHECK:" . Can you produce one from the .c?
You can take example on test/CodeGen/X86/xor.ll ; let me know if you need help on that.

[CSears]

I tried figuring out how to construct a lit test from tst64.ll. I'll try
again.

How does one *attach* a file to review. On Chrome, when I dragged tst64.c
from the finder onto the comment area, as per the dialogs suggestion,
it just opened file:// blah blah /tst64.c as a new page in the browser.

[mehdi_amini]

I always use diff when interacting with Phabricator.
Usually I work locally with git and I generate my diff with it.

If you don’t want to use a VCS, you can look at: http://jungels.net/articles/diff-patch-ten-minutes.html "Creating patches with diff”.

Mehdi

X86ISelLowering.cpp

       RHS = AndLHS.getOperand(1);
     }
 
-    // Use BT if the immediate can't be encoded in a TEST instruction.
-    if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
+    // choosing between BT and TEST for reg,imm
+    //               bit 0-7    bit 8-31     bit 32-63
+    // TEST reg,imm  24b        48b          N/A
+    // BT   reg,imm  32b        32b          40b
+    // TEST AL, AX, EAX and RAX use 8b less
+    // extended registers + bits 32-63 require the REX prefix
+    // for bits 32-63, there is no TESTQ and so BTQ is required
+    const Function *F = DAG.getMachineFunction().getFunction();
+    bool  OptForSize  = F->getAttributes().hasAttribute(
+            AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
+    bool  OptForCold  = F->getAttributes().hasAttribute(
+            AttributeSet::FunctionIndex, Attribute::Cold);
+
+    if (isPowerOf2_64(AndRHSVal) &&
+        (!isUInt<32>(AndRHSVal) ||
+        (!isUInt<16>(AndRHSVal) && (OptForSize | OptForCold)))) {
       LHS = AndLHS;
       RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
     }