[AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract.

[ab]

Summary

This avoids a partial dependency on the previous content of the upper lanes of the destination vector.

[t.p.northover]

Hi Ahmed,

Looks like a good idea to me.

Tim.

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td

 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
 defm : Neon_INS_elt_pattern<v16i8, v8i8,  i32, INSvi8lane>;
 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
 
 
 // Floating point vector extractions are codegen'd as either a sequence of
-// subregister extractions, possibly fed by an INS if the lane number is
-// anything other than zero.
+// subregister extractions, or a MOV (aka CPY here, alias for DUP) if
+// the lane number is anything other than zero.
 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
           (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
           (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
           (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
+
 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
-          (f64 (EXTRACT_SUBREG
-            (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
-                         V128:$Rn, VectorIndexD:$idx),
-            dsub))>;
+          (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
-          (f32 (EXTRACT_SUBREG
-            (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
-                         V128:$Rn, VectorIndexS:$idx),
-            ssub))>;
+          (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
-          (f16 (EXTRACT_SUBREG
-            (INSvi16lane (v8f16 (IMPLICIT_DEF)), 0,
-                         V128:$Rn, VectorIndexH:$idx),
-            hsub))>;
+          (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
 
 // All concat_vectors operations are canonicalised to act on i64 vectors for
 // AArch64. In the general case we need an instruction, which had just as well be
 // INS.
 class ConcatPat<ValueType DstTy, ValueType SrcTy>
   : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
         (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
                      (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;

llvm/trunk/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll

 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
 
 ; DAGCombine to transform a conversion of an extract_vector_elt to an
 ; extract_vector_elt of a conversion, which saves a round trip of copies
 ; of the value to a GPR and back to and FPR.
 ; rdar://11855286
 define double @foo0(<2 x i64> %a) nounwind {
 ; CHECK:  scvtf.2d  [[REG:v[0-9]+]], v0, #9
-; CHECK-NEXT:  ins.d v0[0], [[REG]][1]
+; CHECK-NEXT:  mov  d0, [[REG]][1]
   %vecext = extractelement <2 x i64> %a, i32 1
   %fcvt_n = tail call double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9)
   ret double %fcvt_n
 }
 
 declare double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64, i32) nounwind readnone

llvm/trunk/test/CodeGen/AArch64/arm64-neon-copy.ll

 ; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
   %tmp3 = extractelement <4 x float> %tmp1, i32 2
   %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
   ret <2 x float> %tmp4
 }
 
 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins2f1:
-; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
+; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1]
   %tmp3 = extractelement <2 x double> %tmp1, i32 1
   %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
   ret <1 x double> %tmp4
 }
 
 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
 ; CHECK-LABEL: ins8b8:
 ; CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]

llvm/trunk/test/CodeGen/AArch64/fp16-v8-instructions.ll

 ; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s
 ; CHECK: ins v0.d[1], [[REG]].d[0]
   %1 = fptrunc <8 x float> %a to <8 x half>
   ret <8 x half> %1
 }
 
 define <8 x half> @d_to_h(<8 x double> %a) {
 ; CHECK-LABEL: d_to_h:
-; CHECK-DAG: ins v{{[0-9]+}}.d
-; CHECK-DAG: ins v{{[0-9]+}}.d
-; CHECK-DAG: ins v{{[0-9]+}}.d
-; CHECK-DAG: ins v{{[0-9]+}}.d
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
+; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1]
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h
 ; CHECK-DAG: fcvt h

llvm/trunk/test/CodeGen/AArch64/neon-scalar-copy.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s
 
 define float @test_dup_sv2S(<2 x float> %v) #0 {
  ; CHECK-LABEL: test_dup_sv2S:
- ; CHECK-NEXT: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1]
+ ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
  ; CHECK-NEXT: ret
  %tmp1 = extractelement <2 x float> %v, i32 1
  ret float  %tmp1
 }
 
 define float @test_dup_sv2S_0(<2 x float> %v) #0 {
  ; CHECK-LABEL: test_dup_sv2S_0:
  ; CHECK-NOT: dup {{[vsd][0-9]+}}
  ; CHECK-NOT: ins {{[vsd][0-9]+}}
  ; CHECK-NEXT: ret
  %tmp1 = extractelement <2 x float> %v, i32 0
  ret float  %tmp1
 }
 
 define float @test_dup_sv4S(<4 x float> %v) #0 {
  ; CHECK-LABEL: test_dup_sv4S:
- ; CHECK-NEXT: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1]
+ ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1]
  ; CHECK-NEXT: ret
  %tmp1 = extractelement <4 x float> %v, i32 1
  ret float  %tmp1
 }
 
 define float @test_dup_sv4S_0(<4 x float> %v) #0 {
  ; CHECK-LABEL: test_dup_sv4S_0:
  ; CHECK-NOT: dup {{[vsd][0-9]+}}

  ; CHECK-NOT: ins {{[vsd][0-9]+}}
  ; CHECK-NEXT: ret
  %tmp1 = extractelement <1 x double> %v, i32 0
  ret double  %tmp1
 }
 
 define double @test_dup_dv2D(<2 x double> %v) #0 {
  ; CHECK-LABEL: test_dup_dv2D:
- ; CHECK-NEXT: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
+ ; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1]
  ; CHECK-NEXT: ret
  %tmp1 = extractelement <2 x double> %v, i32 1
  ret double  %tmp1
 }
 
 define double @test_dup_dv2D_0(<2 x double> %v) #0 {
  ; CHECK-LABEL: test_dup_dv2D_0:
  ; CHECK-NOT: dup {{[vsd][0-9]+}}
  ; CHECK-NOT: ins {{[vsd][0-9]+}}
  ; CHECK-NEXT: ret
  %tmp1 = extractelement <2 x double> %v, i32 0
  ret double  %tmp1
 }
 
 define half @test_dup_hv8H(<8 x half> %v) #0 {
  ; CHECK-LABEL: test_dup_hv8H:
- ; CHECK-NEXT: ins {{v[0-9]+}}.h[0], {{v[0-9]+}}.h[1]
+ ; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1]
  ; CHECK-NEXT: ret
  %tmp1 = extractelement <8 x half> %v, i32 1
  ret half  %tmp1
 }
 
 define half @test_dup_hv8H_0(<8 x half> %v) #0 {
  ; CHECK-LABEL: test_dup_hv8H_0:
  ; CHECK-NOT: dup {{[vsdh][0-9]+}}