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Differential D7011

R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
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Authored by arsenm on Jan 15 2015, 3:15 PM.

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arsenm updated this revision to Diff 18270.Jan 15 2015, 3:15 PM
arsenm retitled this revision from to R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32.
arsenm updated this object.
arsenm edited the test plan for this revision. (Show Details)
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arsenm accepted this revision.Jan 15 2015, 4:00 PM
arsenm added a reviewer: arsenm.

r226230

This revision is now accepted and ready to land.Jan 15 2015, 4:00 PM
arsenm closed this revision.Jan 15 2015, 4:00 PM

Revision Contents

PathSize
lib/
Target/
R600/
17 lines
6 lines
test/
CodeGen/
R600/
79 lines
76 lines

Diff 18270

lib/Target/R600/AMDGPUInstructions.td

Show First 20 Lines • Show All 432 Lines • ▼ Show 20 Linesdef FP_ZERO : PatLeaf <
[{return N->getValueAPF().isZero();}] [{return N->getValueAPF().isZero();}]
>; >;
def FP_ONE : PatLeaf < def FP_ONE : PatLeaf <
(fpimm), (fpimm),
[{return N->isExactlyValue(1.0);}] [{return N->isExactlyValue(1.0);}]
>; >;
def FP_HALF : PatLeaf <
(fpimm),
[{return N->isExactlyValue(0.5);}]
>;
let isCodeGenOnly = 1, isPseudo = 1 in { let isCodeGenOnly = 1, isPseudo = 1 in {
let usesCustomInserter = 1 in { let usesCustomInserter = 1 in {
class CLAMP <RegisterClass rc> : AMDGPUShaderInst < class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
(outs rc:$dst), (outs rc:$dst),
(ins rc:$src0), (ins rc:$src0),
"CLAMP $dst, $src0", "CLAMP $dst, $src0",
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
class ROTRPattern <Instruction BIT_ALIGN> : Pat < class ROTRPattern <Instruction BIT_ALIGN> : Pat <
(rotr i32:$src0, i32:$src1), (rotr i32:$src0, i32:$src1),
(BIT_ALIGN $src0, $src0, $src1) (BIT_ALIGN $src0, $src0, $src1)
>; >;
// 24-bit arithmetic patterns // 24-bit arithmetic patterns
def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>; def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
// Special conversion patterns
def cvt_rpi_i32_f32 : PatFrag <
(ops node:$src),
(fp_to_sint (ffloor (fadd $src, FP_HALF)))
>;
def cvt_flr_i32_f32 : PatFrag <
(ops node:$src),
(fp_to_sint (ffloor $src))
>;
/* /*
class UMUL24Pattern <Instruction UMUL24> : Pat < class UMUL24Pattern <Instruction UMUL24> : Pat <
(mul U24:$x, U24:$y), (mul U24:$x, U24:$y),
(UMUL24 $x, $y) (UMUL24 $x, $y)
>; >;
*/ */
class IMad24Pat<Instruction Inst> : Pat < class IMad24Pat<Instruction Inst> : Pat <
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lib/Target/R600/SIInstructions.td

Show First 20 Lines • Show All 1,224 Lines • ▼ Show 20 Lines
>; >;
defm V_MOV_FED_B32 : VOP1Inst <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>; defm V_MOV_FED_B32 : VOP1Inst <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32", defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
VOP_I32_F32, fp_to_f16 VOP_I32_F32, fp_to_f16
>; >;
defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16", defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
VOP_F32_I32, f16_to_fp VOP_F32_I32, f16_to_fp
>; >;
//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "v_cvt_rpi_i32_f32", []>; defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32",
//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "v_cvt_flr_i32_f32", []>; VOP_I32_F32, cvt_rpi_i32_f32>;
defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32",
VOP_I32_F32, cvt_flr_i32_f32>;
//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "v_cvt_off_f32_i4", []>; //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "v_cvt_off_f32_i4", []>;
defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64", defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
VOP_F32_F64, fround VOP_F32_F64, fround
>; >;
defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32", defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
VOP_F64_F32, fextend VOP_F64_F32, fextend
>; >;
defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0", defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
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test/CodeGen/R600/cvt_flr_i32_f32.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.fabs.f32(float) #1
declare float @llvm.floor.f32(float) #1
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_0:
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; SI: s_endpgm
define void @cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
%floor = call float @llvm.floor.f32(float %x) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_1:
; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
; SI: v_cvt_flr_i32_f32_e32 v{{[0-9]+}}, [[TMP]]
; SI: s_endpgm
define void @cvt_flr_i32_f32_1(i32 addrspace(1)* %out, float %x) #0 {
%fadd = fadd float %x, 1.0
%floor = call float @llvm.floor.f32(float %fadd) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs:
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|
; SI: s_endpgm
define void @cvt_flr_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1
%floor = call float @llvm.floor.f32(float %x.fabs) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fneg:
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
; SI: s_endpgm
define void @cvt_flr_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fneg = fsub float -0.000000e+00, %x
%floor = call float @llvm.floor.f32(float %x.fneg) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}cvt_flr_i32_f32_fabs_fneg:
; SI-NOT: add
; SI: v_cvt_flr_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
; SI: s_endpgm
define void @cvt_flr_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1
%x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
%floor = call float @llvm.floor.f32(float %x.fabs.fneg) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}no_cvt_flr_i32_f32_0:
; SI-NOT: v_cvt_flr_i32_f32
; SI: v_floor_f32
; SI: v_cvt_u32_f32_e32
; SI: s_endpgm
define void @no_cvt_flr_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
%floor = call float @llvm.floor.f32(float %x) #1
%cvt = fptoui float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }

test/CodeGen/R600/cvt_rpi_i32_f32.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare float @llvm.fabs.f32(float) #1
declare float @llvm.floor.f32(float) #1
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32:
; SI: v_cvt_rpi_i32_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; SI: s_endpgm
define void @cvt_rpi_i32_f32(i32 addrspace(1)* %out, float %x) #0 {
%fadd = fadd float %x, 0.5
%floor = call float @llvm.floor.f32(float %fadd) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs:
; SI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|{{$}}
; SI: s_endpgm
define void @cvt_rpi_i32_f32_fabs(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1
%fadd = fadd float %x.fabs, 0.5
%floor = call float @llvm.floor.f32(float %fadd) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FIXME: This doesn't work because it forms fsub 0
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fneg:
; XSI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -s{{[0-9]+}}
; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, s{{[0-9]+}}
; SI: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
; SI: s_endpgm
define void @cvt_rpi_i32_f32_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fneg = fsub float -0.000000e+00, %x
%fadd = fadd float %x.fneg, 0.5
%floor = call float @llvm.floor.f32(float %fadd) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FIXME: This doesn't work for same reason as above
; FUNC-LABEL: {{^}}cvt_rpi_i32_f32_fabs_fneg:
; XSI: v_cvt_rpi_i32_f32_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|
; SI: v_sub_f32_e64 [[TMP:v[0-9]+]], 0.5, |s{{[0-9]+}}|
; SI: v_cvt_flr_i32_f32_e32 {{v[0-9]+}}, [[TMP]]
; SI: s_endpgm
define void @cvt_rpi_i32_f32_fabs_fneg(i32 addrspace(1)* %out, float %x) #0 {
%x.fabs = call float @llvm.fabs.f32(float %x) #1
%x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
%fadd = fadd float %x.fabs.fneg, 0.5
%floor = call float @llvm.floor.f32(float %fadd) #1
%cvt = fptosi float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}no_cvt_rpi_i32_f32_0:
; SI-NOT: v_cvt_rpi_i32_f32
; SI: v_add_f32
; SI: v_floor_f32
; SI: v_cvt_u32_f32
; SI: s_endpgm
define void @no_cvt_rpi_i32_f32_0(i32 addrspace(1)* %out, float %x) #0 {
%fadd = fadd float %x, 0.5
%floor = call float @llvm.floor.f32(float %fadd) #1
%cvt = fptoui float %floor to i32
store i32 %cvt, i32 addrspace(1)* %out
ret void
}
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }