AArch64: Relax assert about large shift sizes.

[MatzeB]

Summary

Shift sizes larger than the size of the value in bits can happen if
constant folding fails.

Testcase based on rdar://19211454

[qcolombet]

Hi Matthias,

I am wondering if we shouldn’t generate an undef node in Selection DAG for such shifts, unless the semantic is properly defined there.

What do you think?

[ab]

So.. I'm curious, what happens now? (i.e.: how about a little more explicit testcase?)
I guess since it's undefined, we care even less anyway..

Also, you mention it in the comment: I would have expected this to be folded to undef, why didn't it?

-Ahmed

[MatzeB]

The radar mentions "llvm-stress --seed=29856" as the source of that program, maybe that just doesn't perform any combining/constant folding. In each case I don't know if we should always rely on constant folding/combining happening, what is with clang -O0 for example?
In any case having an instruction with an undefined result in the IR is no reason for a target to fail an assertion IMO.

Greeting
Matthias

[MatzeB]

Abandoning in favor of http://reviews.llvm.org/D6946

[qcolombet]

Hi Matthias,

llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
     // The resulting code will be at least as good as the original one
     // plus it may expose more opportunities for bitfield insert pattern.
     // FIXME: Currently we limit this to the bigger pattern, because
     // some optimizations expect AND and not UBFM
     Opd0 = N->getOperand(0);
   } else
     return false;
 
-  assert((BiggerPattern || (Srl_imm > 0 && Srl_imm < VT.getSizeInBits())) &&
-         "bad amount in shift node!");
+  // Bail out on large immediates. This happens when no proper
+  // combining/constant folding was performed.
+  if (!BiggerPattern && (Srl_imm <= 0 || Srl_imm >= VT.getSizeInBits()))
+    return false;
 
   LSB = Srl_imm;
   MSB = Srl_imm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(And_imm)
                                   : countTrailingOnes<uint64_t>(And_imm)) -
         1;
   if (ClampMSB)
     // Since we're moving the extend before the right shift operation, we need
     // to clamp the MSB to make sure we don't shift in undefined bits instead of
static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
   } else if (BiggerPattern) {
     // Let's pretend a 0 shift left has been performed.
     // FIXME: Currently we limit this to the bigger pattern case,
     // because some optimizations expect AND and not UBFM
     Opd0 = N->getOperand(0);
   } else
     return false;
 
-  assert(Shl_imm < VT.getSizeInBits() && "bad amount in shift node!");
+  // Missing combines/constant folding may have left us with strange
+  // constants.
+  if (Shl_imm >= VT.getSizeInBits())
+    return false;
+
   uint64_t Srl_imm = 0;
   if (!isIntImmediate(N->getOperand(1), Srl_imm))
     return false;
 
   assert(Srl_imm > 0 && Srl_imm < VT.getSizeInBits() &&
          "bad amount in shift node!");
   // Note: The width operand is encoded as width-1.
   unsigned Width = VT.getSizeInBits() - Trunc_bits - Srl_imm - 1;

llvm/trunk/test/CodeGen/AArch64/large_shift.ll

+; RUN: llc -march=aarch64 -o - %s
+target triple = "arm64-unknown-unknown"
+
+; Make sure we don't run into an assert in the aarch64 code selection when
+; DAGCombining fails.
+
+declare void @t()
+
+define void @foo() {
+  %c = bitcast i64 270458 to i64
+  %t0 = lshr i64 %c, 422383
+  %t1 = trunc i64 %t0 to i1
+  br i1 %t1, label %BB1, label %BB0
+
+BB0:
+  call void @t()
+  br label %BB1
+
+BB1:
+  ret void
+}