[AArch64] Fix the bug PR21675 about lowering llvm.ctpop.i32

[• HaoLiu]

Summary

Hi Tim and other reviewers,

This patch fix the bug PR21675 (http://llvm.org/bugs/show_bug.cgi?id=21675). There is a bug about lowering llvm.ctpop.i32. Previously we use:

SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8)

But ctpop is to do bit count. Using undef doesn't mean the upper bits are all zero.

There are some redundant instructions as follows:

fmov w0, s0
fmov d0, x0

But this should be optimized in other places.

This patch is by Wei-cheng Wang. Review please.

Thanks,
-Hao

[• HaoLiu]

ping...

As this is sent around Christmas holiday, maybe there is no one noticed this bug fix.

Thanks,
-Hao

[• HaoLiu]

Committed in rL227550.

lib/Target/AArch64/AArch64ISelLowering.cpp

SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
   // the AdvSIMD registers are cheap.
   //  FMOV    D0, X0        // copy 64-bit int to vector, high bits zero'd
   //  CNT     V0.8B, V0.8B  // 8xbyte pop-counts
   //  ADDV    B0, V0.8B     // sum 8xbyte pop-counts
   //  UMOV    X0, V0.B[0]   // copy byte result back to integer reg
   SDValue Val = Op.getOperand(0);
   SDLoc DL(Op);
   EVT VT = Op.getValueType();
-  SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
 
-  SDValue VecVal;
-  if (VT == MVT::i32) {
-    VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
-    VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
-                                       VecVal);
-  } else {
-    VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
-  }
+  if (VT == MVT::i32)
+    Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
+  Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
 
-  SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
+  SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
   SDValue UaddLV = DAG.getNode(
       ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
       DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
 
   if (VT == MVT::i64)
     UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
   return UaddLV;
 }

test/CodeGen/AArch64/arm64-popcnt.ll

 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
 ; RUN: llc < %s -march=aarch64 -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s
 
 define i32 @cnt32_advsimd(i32 %x) nounwind readnone {
   %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %cnt
-; CHECK: fmov s0, w0
+; CHECK: ubfx x{{[0-9]+}}
+; CHECK: fmov d0, x{{[0-9]+}}
 ; CHECK: cnt.8b v0, v0
 ; CHECK: uaddlv.8b  h0, v0
 ; CHECK: fmov w0, s0
 ; CHECK: ret
 ; CHECK-NONEON-LABEL: cnt32_advsimd
 ; CHECK-NONEON-NOT: 8b
 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x55555555
 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x33333333
 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0xf0f0f0f
 ; CHECK-NONEON: mul
+}
 
+define i32 @cnt32_advsimd_2(<2 x i32> %x) {
+  %1 = extractelement <2 x i32> %x, i64 0
+  %2 = tail call i32 @llvm.ctpop.i32(i32 %1)
+  ret i32 %2
+; CHECK: fmov w0, s0
+; CHECK: fmov d0, x0
+; CHECK: cnt.8b v0, v0
+; CHECK: uaddlv.8b  h0, v0
+; CHECK: fmov w0, s0
+; CHECK: ret
+; CHECK-NONEON-LABEL: cnt32_advsimd_2
+; CHECK-NONEON-NOT: 8b
+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x55555555
+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x33333333
+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0xf0f0f0f
+; CHECK-NONEON: mul
 }
 
 define i64 @cnt64_advsimd(i64 %x) nounwind readnone {
   %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
   ret i64 %cnt
 ; CHECK: fmov d0, x0
 ; CHECK: cnt.8b v0, v0
 ; CHECK: uaddlv.8b  h0, v0