[mips] Reserve $at and use it for frame pointer elimination.

[vstefanovic]

Summary

When spilling a register, RegScavenger calls MipsSERegisterInfo::eliminateFI(),
which needs a free register to handle offsets over 16 bits, resulting in
"Cannot scavenge register without an emergency spill slot!" assert.
This patch puts $at on the reserved registers list, and uses it in eliminateFI()
instead of requesting a register from RegScavenger.

[vstefanovic]

When RegScavenger runs out of registers, it tries to spill one. So it generates
e.g.

SW %RA<kill>, <fi#11>, 0

which is converted by eliminateFI() into:

SW %RA<kill>, %FP, Offset

for offsets that fit into 16 bits. Otherwise, we need yet another register:

%vreg79<def> = LUi 1
%vreg79<def> = ADDu %FP, %vreg79<kill>
SW %RA<kill>, %vreg79<kill>, 120

Then RegScavenger is called to provide a register for vreg79, so it asserts with
"Cannot scavenge register without an emergency spill slot!".

There is a number of mips tests that fail when $at is reserved, because they
have hardcoded expected register values, and will have to be fixed if this
patch gets accepted.

[vstefanovic]

Minimal c code to reproduce the error, used to generate vector-multiply.ll
from the patch:

#include <stdint.h>
typedef int8_t VI8 attribute((vector_size(16)));

int main(int argc, char** argh) {

VI8 v0 = (VI8) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
VI8 v1 = (VI8) {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int unused_variable[16384];
VI8 result = v0*v1;
return 0;

}

Built with:
clang -S -emit-llvm vector-multiply.c -o vector-multiply.ll -O0

[dsanders]

This patch unconditionally reserves a register in order to support the fairly rare case of a stack frame being larger than 64KB. My starting position is that this isn't the right thing to do

Why not create an emergency spill slot for the register scavenger to use when the stack frame is large? This should allow it to cope with this rare case without limiting the optimization of the common cases.

[vstefanovic]

Abandoned in favour of http://reviews.llvm.org/D8895 .

lib/Target/Mips/MipsRegisterInfo.cpp

 
 const uint32_t *MipsRegisterInfo::getMips16RetHelperMask() {
   return CSR_Mips16RetHelper_RegMask;
 }
 
 BitVector MipsRegisterInfo::
 getReservedRegs(const MachineFunction &MF) const {
   static const MCPhysReg ReservedGPR32[] = {
-    Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
+    Mips::ZERO, Mips::K0, Mips::K1, Mips::SP, Mips::AT
   };
 
   static const MCPhysReg ReservedGPR64[] = {
-    Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
+    Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64, Mips::AT_64
   };
 
   BitVector Reserved(getNumRegs());
   typedef TargetRegisterClass::const_iterator RegIter;
 
   for (unsigned I = 0; I < array_lengthof(ReservedGPR32); ++I)
     Reserved.set(ReservedGPR32[I]);
 

lib/Target/Mips/MipsSERegisterInfo.cpp

 
   // Calculate final offset.
   // - There is no need to change the offset if the frame object is one of the
   //   following: an outgoing argument, pointer to a dynamically allocated
   //   stack space or a $gp restore location,
   // - If the frame object is any of the following, its offset must be adjusted
   //   by adding the size of the stack:
   //   incoming argument, callee-saved register location or local variable.
-  bool IsKill = false;
   int64_t Offset;
 
   Offset = SPOffset + (int64_t)StackSize;
   Offset += MI.getOperand(OpNo + 1).getImm();
 
   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
 
   if (!MI.isDebugValue()) {
     // Make sure Offset fits within the field available.
     // For MSA instructions, this is a 10-bit signed immediate (scaled by
     // element size), otherwise it is a 16-bit signed immediate.
     unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
     unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
 
     if (OffsetBitSize < 16 && isInt<16>(Offset) &&
         (!isIntN(OffsetBitSize, Offset) ||
          OffsetToAlignment(Offset, OffsetAlign) != 0)) {
       // If we have an offset that needs to fit into a signed n-bit immediate
       // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
       MachineBasicBlock &MBB = *MI.getParent();
       DebugLoc DL = II->getDebugLoc();
       unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
-      const TargetRegisterClass *RC =
-          Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
-      MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
-      unsigned Reg = RegInfo.createVirtualRegister(RC);
+      unsigned AT = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
       const MipsSEInstrInfo &TII =
           *static_cast<const MipsSEInstrInfo *>(
               MBB.getParent()->getSubtarget().getInstrInfo());
-      BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
+      BuildMI(MBB, II, DL, TII.get(ADDiu), AT).addReg(FrameReg).addImm(Offset);
 
-      FrameReg = Reg;
+      FrameReg = AT;
       Offset = 0;
-      IsKill = true;
     } else if (!isInt<16>(Offset)) {
       // Otherwise split the offset into 16-bit pieces and add it in multiple
       // instructions.
       MachineBasicBlock &MBB = *MI.getParent();
       DebugLoc DL = II->getDebugLoc();
       unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
-      unsigned NewImm = 0;
+      unsigned AT = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT;
+      unsigned LUi = Subtarget.isABI_N64() ? Mips::LUi64 : Mips::LUi;
+
+      int64_t Hi = (Offset + (1 << 15)) >> 16;
+      Offset -= (Hi << 16);
+
       const MipsSEInstrInfo &TII =
           *static_cast<const MipsSEInstrInfo *>(
               MBB.getParent()->getSubtarget().getInstrInfo());
-      unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
-                                       OffsetBitSize == 16 ? &NewImm : nullptr);
-      BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
-        .addReg(Reg, RegState::Kill);
-
-      FrameReg = Reg;
-      Offset = SignExtend64<16>(NewImm);
-      IsKill = true;
+      BuildMI(MBB, II, DL, TII.get(LUi), AT).addImm(Hi);
+      BuildMI(MBB, II, DL, TII.get(ADDu), AT).addReg(FrameReg).addReg(AT);
+
+      FrameReg = AT;
     }
   }
 
-  MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
+  MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false);
   MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
 }

test/CodeGen/Mips/vector-multiply.ll

+; RUN: llc -march=mipsel -O0 < %s
+; RUN: llc -march=mips64el -O0 < %s
+
+define i32 @main(i32 %argc, i8** %argh) "no-frame-pointer-elim"="true" {
+entry:
+  %retval = alloca i32, align 4
+  %argc.addr = alloca i32, align 4
+  %argh.addr = alloca i8**, align 8
+  %v0 = alloca <16 x i8>, align 16
+  %.compoundliteral = alloca <16 x i8>, align 16
+  %v1 = alloca <16 x i8>, align 16
+  %.compoundliteral1 = alloca <16 x i8>, align 16
+  %unused_variable = alloca [16384 x i32], align 16
+  %result = alloca <16 x i8>, align 16
+  store i32 0, i32* %retval
+  store i32 %argc, i32* %argc.addr, align 4
+  store i8** %argh, i8*** %argh.addr, align 8
+  store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
+  %0 = load <16 x i8>* %.compoundliteral
+  store <16 x i8> %0, <16 x i8>* %v0, align 16
+  store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
+  %1 = load <16 x i8>* %.compoundliteral1
+  store <16 x i8> %1, <16 x i8>* %v1, align 16
+  %2 = load <16 x i8>* %v0, align 16
+  %3 = load <16 x i8>* %v1, align 16
+  %mul = mul <16 x i8> %2, %3
+  store <16 x i8> %mul, <16 x i8>* %result, align 16
+  ret i32 0
+}
+