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[Mips] Return false for isFPCloseToIncomingSP()
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Authored by vradosavljevic on Apr 8 2015, 7:03 AM.

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dsanders
petarj

Summary

On Mips, frame pointer points to the same side of the frame as the stack pointer.
This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and was to far away from $fp if frame is larger than 2^15 bytes.

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vradosavljevic updated this revision to Diff 23415.Apr 8 2015, 7:03 AM

vradosavljevic retitled this revision from to [Mips] Return false for isFPCloseToIncomingSP().

vradosavljevic updated this object.

vradosavljevic edited the test plan for this revision. (Show Details)

vradosavljevic added reviewers: petarj, dsanders.

vradosavljevic set the repository for this revision to rL LLVM.

vradosavljevic added a subscriber: Unknown Object (MLST).

vkalintiris added a subscriber: vkalintiris.Apr 15 2015, 3:17 AM

Ping.

dsanders added inline comments.Apr 20 2015, 8:59 AM

test/CodeGen/Mips/vector-multiply.ll
1 ↗	(On Diff #23415)	Please add some checks on the output (with FileCheck). At the moment it's only testing that llc doesn't crash or fail.

Comment addressed.

vradosavljevic added inline comments.Apr 22 2015, 7:51 AM

test/CodeGen/Mips/vector-multiply.ll
1 ↗	(On Diff #23415)	Done.

Ping.

Is this ok to commit?

LGTM. Sorry for the delays

This revision is now accepted and ready to land.May 12 2015, 9:04 AM

Committed as r237153.

Revision Contents

Path

Size

lib/

Target/

Mips/

MipsFrameLowering.h

2 lines

test/

CodeGen/

Mips/

emergency-spill-slot-near-fp.ll

32 lines

Diff 24227

lib/Target/Mips/MipsFrameLowering.h

	Show All 26 Lines
	public:			public:
	explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment)			explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment)
	: TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}			: TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {}

	static const MipsFrameLowering *create(const MipsSubtarget &ST);			static const MipsFrameLowering *create(const MipsSubtarget &ST);

	bool hasFP(const MachineFunction &MF) const override;			bool hasFP(const MachineFunction &MF) const override;

				bool isFPCloseToIncomingSP() const override { return false; }

	void			void
	eliminateCallFramePseudoInstr(MachineFunction &MF,			eliminateCallFramePseudoInstr(MachineFunction &MF,
	MachineBasicBlock &MBB,			MachineBasicBlock &MBB,
	MachineBasicBlock::iterator I) const override;			MachineBasicBlock::iterator I) const override;

	protected:			protected:
	uint64_t estimateStackSize(const MachineFunction &MF) const;			uint64_t estimateStackSize(const MachineFunction &MF) const;
	};			};

	/// Create MipsFrameLowering objects.			/// Create MipsFrameLowering objects.
	const MipsFrameLowering *createMips16FrameLowering(const MipsSubtarget &ST);			const MipsFrameLowering *createMips16FrameLowering(const MipsSubtarget &ST);
	const MipsFrameLowering *createMipsSEFrameLowering(const MipsSubtarget &ST);			const MipsFrameLowering *createMipsSEFrameLowering(const MipsSubtarget &ST);

	} // End llvm namespace			} // End llvm namespace

	#endif			#endif

test/CodeGen/Mips/emergency-spill-slot-near-fp.ll

This file was added.

				; Check that register scavenging spill slot is close to $fp.
				; RUN: llc -march=mipsel -O0 < %s \| FileCheck %s

				; CHECK: sw ${{.*}}, 4($fp)
				; CHECK: lw ${{.*}}, 4($fp)

				define i32 @main(i32 signext %argc, i8** %argv) "no-frame-pointer-elim"="true" {
				entry:
				%retval = alloca i32, align 4
				%argc.addr = alloca i32, align 4
				%argv.addr = alloca i8**, align 4
				%v0 = alloca <16 x i8>, align 16
				%.compoundliteral = alloca <16 x i8>, align 16
				%v1 = alloca <16 x i8>, align 16
				%.compoundliteral1 = alloca <16 x i8>, align 16
				%unused_variable = alloca [16384 x i32], align 4
				%result = alloca <16 x i8>, align 16
				store i32 0, i32* %retval
				store i32 %argc, i32* %argc.addr, align 4
				store i8 %argv, i8* %argv.addr, align 4
				store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
				%0 = load <16 x i8>, <16 x i8>* %.compoundliteral
				store <16 x i8> %0, <16 x i8>* %v0, align 16
				store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
				%1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
				store <16 x i8> %1, <16 x i8>* %v1, align 16
				%2 = load <16 x i8>, <16 x i8>* %v0, align 16
				%3 = load <16 x i8>, <16 x i8>* %v1, align 16
				%mul = mul <16 x i8> %2, %3
				store <16 x i8> %mul, <16 x i8>* %result, align 16
				ret i32 0
				}