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Differential D6448

Fix wrong encoding of MRSBanked.
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Authored by • chatur01 on Nov 28 2014, 5:26 AM.
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Event Timeline

• chatur01 updated this revision to Diff 16725.Nov 28 2014, 5:26 AM
• chatur01 retitled this revision from to Fix wrong encoding of MRSBanked..
• chatur01 updated this object.
• chatur01 edited the test plan for this revision. (Show Details)
• chatur01 set the repository for this revision to rL LLVM.
• chatur01 updated this revision to Diff 16731.Nov 28 2014, 6:34 AM

More context.

t.p.northover added a subscriber: Unknown Object (MLST).Nov 28 2014, 6:47 AM
t.p.northover added a subscriber: t.p.northover.

Adding llvm-commits.

t.p.northover added a comment.Nov 28 2014, 6:49 AM

Hi Charlie,

This looks fine to me. Thanks for spotting it!

Tim.

• chatur01 added a comment.Nov 28 2014, 7:02 AM
In D6448#8, @t.p.northover wrote:

Hi Charlie,

This looks fine to me. Thanks for spotting it!

Tim.

Thanks for the review Tim :) -- committed as r222920.

Patch by Matthew Wahab, forgot to mention that at the start.

Best,
Charlie.

Revision Contents

PathSize
lib/
Target/
ARM/
2 lines
test/
MC/
ARM/
66 lines
Disassembler/
ARM/
66 lines

Diff 16731

lib/Target/ARM/ARMInstrInfo.td

Show First 20 Lines • Show All 5,068 Lines • ▼ Show 20 Lines
def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked),
NoItinerary, "mrs", "\t$Rd, $banked", []>, NoItinerary, "mrs", "\t$Rd, $banked", []>,
Requires<[IsARM, HasVirtualization]> { Requires<[IsARM, HasVirtualization]> {
bits<6> banked; bits<6> banked;
bits<4> Rd; bits<4> Rd;
let Inst{23} = 0; let Inst{23} = 0;
let Inst{22} = banked{5}; // R bit let Inst{22} = banked{5}; // R bit
let Inst{21-20} = 0b10; let Inst{21-20} = 0b00;
let Inst{19-16} = banked{3-0}; let Inst{19-16} = banked{3-0};
let Inst{15-12} = Rd; let Inst{15-12} = Rd;
let Inst{11-9} = 0b001; let Inst{11-9} = 0b001;
let Inst{8} = banked{4}; let Inst{8} = banked{4};
let Inst{7-0} = 0b00000000; let Inst{7-0} = 0b00000000;
} }
// Move from ARM core register to Special Register // Move from ARM core register to Special Register
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test/MC/ARM/move-banked-regs.s

@ RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM @ RUN: llvm-mc -triple armv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-ARM
@ RUN: llvm-mc -triple thumbv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-THUMB @ RUN: llvm-mc -triple thumbv7 -mattr=virtualization -show-encoding %s | FileCheck %s --check-prefix=CHECK-THUMB
mrs r2, r8_usr mrs r2, r8_usr
mrs r3, r9_usr mrs r3, r9_usr
mrs r5, r10_usr mrs r5, r10_usr
mrs r7, r11_usr mrs r7, r11_usr
mrs r11, r12_usr mrs r11, r12_usr
mrs r1, sp_usr mrs r1, sp_usr
mrs r2, lr_usr mrs r2, lr_usr
@ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x20,0xe1] @ CHECK-ARM: mrs r2, r8_usr @ encoding: [0x00,0x22,0x00,0xe1]
@ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x21,0xe1] @ CHECK-ARM: mrs r3, r9_usr @ encoding: [0x00,0x32,0x01,0xe1]
@ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x22,0xe1] @ CHECK-ARM: mrs r5, r10_usr @ encoding: [0x00,0x52,0x02,0xe1]
@ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x23,0xe1] @ CHECK-ARM: mrs r7, r11_usr @ encoding: [0x00,0x72,0x03,0xe1]
@ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x24,0xe1] @ CHECK-ARM: mrs r11, r12_usr @ encoding: [0x00,0xb2,0x04,0xe1]
@ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x25,0xe1] @ CHECK-ARM: mrs r1, sp_usr @ encoding: [0x00,0x12,0x05,0xe1]
@ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x26,0xe1] @ CHECK-ARM: mrs r2, lr_usr @ encoding: [0x00,0x22,0x06,0xe1]
@ CHECK-THUMB: mrs r2, r8_usr @ encoding: [0xe0,0xf3,0x20,0x82] @ CHECK-THUMB: mrs r2, r8_usr @ encoding: [0xe0,0xf3,0x20,0x82]
@ CHECK-THUMB: mrs r3, r9_usr @ encoding: [0xe1,0xf3,0x20,0x83] @ CHECK-THUMB: mrs r3, r9_usr @ encoding: [0xe1,0xf3,0x20,0x83]
@ CHECK-THUMB: mrs r5, r10_usr @ encoding: [0xe2,0xf3,0x20,0x85] @ CHECK-THUMB: mrs r5, r10_usr @ encoding: [0xe2,0xf3,0x20,0x85]
@ CHECK-THUMB: mrs r7, r11_usr @ encoding: [0xe3,0xf3,0x20,0x87] @ CHECK-THUMB: mrs r7, r11_usr @ encoding: [0xe3,0xf3,0x20,0x87]
@ CHECK-THUMB: mrs r11, r12_usr @ encoding: [0xe4,0xf3,0x20,0x8b] @ CHECK-THUMB: mrs r11, r12_usr @ encoding: [0xe4,0xf3,0x20,0x8b]
@ CHECK-THUMB: mrs r1, sp_usr @ encoding: [0xe5,0xf3,0x20,0x81] @ CHECK-THUMB: mrs r1, sp_usr @ encoding: [0xe5,0xf3,0x20,0x81]
@ CHECK-THUMB: mrs r2, lr_usr @ encoding: [0xe6,0xf3,0x20,0x82] @ CHECK-THUMB: mrs r2, lr_usr @ encoding: [0xe6,0xf3,0x20,0x82]
mrs r2, r8_fiq mrs r2, r8_fiq
mrs r3, r9_fiq mrs r3, r9_fiq
mrs r5, r10_fiq mrs r5, r10_fiq
mrs r7, r11_fiq mrs r7, r11_fiq
mrs r11, r12_fiq mrs r11, r12_fiq
mrs r1, sp_fiq mrs r1, sp_fiq
mrs r2, lr_fiq mrs r2, lr_fiq
mrs r3, spsr_fiq mrs r3, spsr_fiq
@ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x28,0xe1] @ CHECK-ARM: mrs r2, r8_fiq @ encoding: [0x00,0x22,0x08,0xe1]
@ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x29,0xe1] @ CHECK-ARM: mrs r3, r9_fiq @ encoding: [0x00,0x32,0x09,0xe1]
@ CHECK-ARM: mrs r5, r10_fiq @ encoding: [0x00,0x52,0x2a,0xe1] @ CHECK-ARM: mrs r5, r10_fiq @ encoding: [0x00,0x52,0x0a,0xe1]
@ CHECK-ARM: mrs r7, r11_fiq @ encoding: [0x00,0x72,0x2b,0xe1] @ CHECK-ARM: mrs r7, r11_fiq @ encoding: [0x00,0x72,0x0b,0xe1]
@ CHECK-ARM: mrs r11, r12_fiq @ encoding: [0x00,0xb2,0x2c,0xe1] @ CHECK-ARM: mrs r11, r12_fiq @ encoding: [0x00,0xb2,0x0c,0xe1]
@ CHECK-ARM: mrs r1, sp_fiq @ encoding: [0x00,0x12,0x2d,0xe1] @ CHECK-ARM: mrs r1, sp_fiq @ encoding: [0x00,0x12,0x0d,0xe1]
@ CHECK-ARM: mrs r2, lr_fiq @ encoding: [0x00,0x22,0x2e,0xe1] @ CHECK-ARM: mrs r2, lr_fiq @ encoding: [0x00,0x22,0x0e,0xe1]
@ CHECK-ARM: mrs r3, SPSR_fiq @ encoding: [0x00,0x32,0x6e,0xe1] @ CHECK-ARM: mrs r3, SPSR_fiq @ encoding: [0x00,0x32,0x4e,0xe1]
@ CHECK-THUMB: mrs r2, r8_fiq @ encoding: [0xe8,0xf3,0x20,0x82] @ CHECK-THUMB: mrs r2, r8_fiq @ encoding: [0xe8,0xf3,0x20,0x82]
@ CHECK-THUMB: mrs r3, r9_fiq @ encoding: [0xe9,0xf3,0x20,0x83] @ CHECK-THUMB: mrs r3, r9_fiq @ encoding: [0xe9,0xf3,0x20,0x83]
@ CHECK-THUMB: mrs r5, r10_fiq @ encoding: [0xea,0xf3,0x20,0x85] @ CHECK-THUMB: mrs r5, r10_fiq @ encoding: [0xea,0xf3,0x20,0x85]
@ CHECK-THUMB: mrs r7, r11_fiq @ encoding: [0xeb,0xf3,0x20,0x87] @ CHECK-THUMB: mrs r7, r11_fiq @ encoding: [0xeb,0xf3,0x20,0x87]
@ CHECK-THUMB: mrs r11, r12_fiq @ encoding: [0xec,0xf3,0x20,0x8b] @ CHECK-THUMB: mrs r11, r12_fiq @ encoding: [0xec,0xf3,0x20,0x8b]
@ CHECK-THUMB: mrs r1, sp_fiq @ encoding: [0xed,0xf3,0x20,0x81] @ CHECK-THUMB: mrs r1, sp_fiq @ encoding: [0xed,0xf3,0x20,0x81]
@ CHECK-THUMB: mrs r2, lr_fiq @ encoding: [0xee,0xf3,0x20,0x82] @ CHECK-THUMB: mrs r2, lr_fiq @ encoding: [0xee,0xf3,0x20,0x82]
@ CHECK-THUMB: mrs r3, SPSR_fiq @ encoding: [0xfe,0xf3,0x20,0x83] @ CHECK-THUMB: mrs r3, SPSR_fiq @ encoding: [0xfe,0xf3,0x20,0x83]
mrs r4, lr_irq mrs r4, lr_irq
mrs r9, sp_irq mrs r9, sp_irq
mrs r1, spsr_irq mrs r1, spsr_irq
@ CHECK-ARM: mrs r4, lr_irq @ encoding: [0x00,0x43,0x20,0xe1] @ CHECK-ARM: mrs r4, lr_irq @ encoding: [0x00,0x43,0x00,0xe1]
@ CHECK-ARM: mrs r9, sp_irq @ encoding: [0x00,0x93,0x21,0xe1] @ CHECK-ARM: mrs r9, sp_irq @ encoding: [0x00,0x93,0x01,0xe1]
@ CHECK-ARM: mrs r1, SPSR_irq @ encoding: [0x00,0x13,0x60,0xe1] @ CHECK-ARM: mrs r1, SPSR_irq @ encoding: [0x00,0x13,0x40,0xe1]
@ CHECK-THUMB: mrs r4, lr_irq @ encoding: [0xe0,0xf3,0x30,0x84] @ CHECK-THUMB: mrs r4, lr_irq @ encoding: [0xe0,0xf3,0x30,0x84]
@ CHECK-THUMB: mrs r9, sp_irq @ encoding: [0xe1,0xf3,0x30,0x89] @ CHECK-THUMB: mrs r9, sp_irq @ encoding: [0xe1,0xf3,0x30,0x89]
@ CHECK-THUMB: mrs r1, SPSR_irq @ encoding: [0xf0,0xf3,0x30,0x81] @ CHECK-THUMB: mrs r1, SPSR_irq @ encoding: [0xf0,0xf3,0x30,0x81]
mrs r1, lr_svc mrs r1, lr_svc
mrs r3, sp_svc mrs r3, sp_svc
mrs r5, spsr_svc mrs r5, spsr_svc
@ CHECK-ARM: mrs r1, lr_svc @ encoding: [0x00,0x13,0x22,0xe1] @ CHECK-ARM: mrs r1, lr_svc @ encoding: [0x00,0x13,0x02,0xe1]
@ CHECK-ARM: mrs r3, sp_svc @ encoding: [0x00,0x33,0x23,0xe1] @ CHECK-ARM: mrs r3, sp_svc @ encoding: [0x00,0x33,0x03,0xe1]
@ CHECK-ARM: mrs r5, SPSR_svc @ encoding: [0x00,0x53,0x62,0xe1] @ CHECK-ARM: mrs r5, SPSR_svc @ encoding: [0x00,0x53,0x42,0xe1]
@ CHECK-THUMB: mrs r1, lr_svc @ encoding: [0xe2,0xf3,0x30,0x81] @ CHECK-THUMB: mrs r1, lr_svc @ encoding: [0xe2,0xf3,0x30,0x81]
@ CHECK-THUMB: mrs r3, sp_svc @ encoding: [0xe3,0xf3,0x30,0x83] @ CHECK-THUMB: mrs r3, sp_svc @ encoding: [0xe3,0xf3,0x30,0x83]
@ CHECK-THUMB: mrs r5, SPSR_svc @ encoding: [0xf2,0xf3,0x30,0x85] @ CHECK-THUMB: mrs r5, SPSR_svc @ encoding: [0xf2,0xf3,0x30,0x85]
mrs r5, lr_abt mrs r5, lr_abt
mrs r7, sp_abt mrs r7, sp_abt
mrs r9, spsr_abt mrs r9, spsr_abt
@ CHECK-ARM: mrs r5, lr_abt @ encoding: [0x00,0x53,0x24,0xe1] @ CHECK-ARM: mrs r5, lr_abt @ encoding: [0x00,0x53,0x04,0xe1]
@ CHECK-ARM: mrs r7, sp_abt @ encoding: [0x00,0x73,0x25,0xe1] @ CHECK-ARM: mrs r7, sp_abt @ encoding: [0x00,0x73,0x05,0xe1]
@ CHECK-ARM: mrs r9, SPSR_abt @ encoding: [0x00,0x93,0x64,0xe1] @ CHECK-ARM: mrs r9, SPSR_abt @ encoding: [0x00,0x93,0x44,0xe1]
@ CHECK-THUMB: mrs r5, lr_abt @ encoding: [0xe4,0xf3,0x30,0x85] @ CHECK-THUMB: mrs r5, lr_abt @ encoding: [0xe4,0xf3,0x30,0x85]
@ CHECK-THUMB: mrs r7, sp_abt @ encoding: [0xe5,0xf3,0x30,0x87] @ CHECK-THUMB: mrs r7, sp_abt @ encoding: [0xe5,0xf3,0x30,0x87]
@ CHECK-THUMB: mrs r9, SPSR_abt @ encoding: [0xf4,0xf3,0x30,0x89] @ CHECK-THUMB: mrs r9, SPSR_abt @ encoding: [0xf4,0xf3,0x30,0x89]
mrs r9, lr_und mrs r9, lr_und
mrs r11, sp_und mrs r11, sp_und
mrs r12, spsr_und mrs r12, spsr_und
@ CHECK-ARM: mrs r9, lr_und @ encoding: [0x00,0x93,0x26,0xe1] @ CHECK-ARM: mrs r9, lr_und @ encoding: [0x00,0x93,0x06,0xe1]
@ CHECK-ARM: mrs r11, sp_und @ encoding: [0x00,0xb3,0x27,0xe1] @ CHECK-ARM: mrs r11, sp_und @ encoding: [0x00,0xb3,0x07,0xe1]
@ CHECK-ARM: mrs r12, SPSR_und @ encoding: [0x00,0xc3,0x66,0xe1] @ CHECK-ARM: mrs r12, SPSR_und @ encoding: [0x00,0xc3,0x46,0xe1]
@ CHECK-THUMB: mrs r9, lr_und @ encoding: [0xe6,0xf3,0x30,0x89] @ CHECK-THUMB: mrs r9, lr_und @ encoding: [0xe6,0xf3,0x30,0x89]
@ CHECK-THUMB: mrs r11, sp_und @ encoding: [0xe7,0xf3,0x30,0x8b] @ CHECK-THUMB: mrs r11, sp_und @ encoding: [0xe7,0xf3,0x30,0x8b]
@ CHECK-THUMB: mrs r12, SPSR_und @ encoding: [0xf6,0xf3,0x30,0x8c] @ CHECK-THUMB: mrs r12, SPSR_und @ encoding: [0xf6,0xf3,0x30,0x8c]
mrs r2, lr_mon mrs r2, lr_mon
mrs r4, sp_mon mrs r4, sp_mon
mrs r6, spsr_mon mrs r6, spsr_mon
@ CHECK-ARM: mrs r2, lr_mon @ encoding: [0x00,0x23,0x2c,0xe1] @ CHECK-ARM: mrs r2, lr_mon @ encoding: [0x00,0x23,0x0c,0xe1]
@ CHECK-ARM: mrs r4, sp_mon @ encoding: [0x00,0x43,0x2d,0xe1] @ CHECK-ARM: mrs r4, sp_mon @ encoding: [0x00,0x43,0x0d,0xe1]
@ CHECK-ARM: mrs r6, SPSR_mon @ encoding: [0x00,0x63,0x6c,0xe1] @ CHECK-ARM: mrs r6, SPSR_mon @ encoding: [0x00,0x63,0x4c,0xe1]
@ CHECK-THUMB: mrs r2, lr_mon @ encoding: [0xec,0xf3,0x30,0x82] @ CHECK-THUMB: mrs r2, lr_mon @ encoding: [0xec,0xf3,0x30,0x82]
@ CHECK-THUMB: mrs r4, sp_mon @ encoding: [0xed,0xf3,0x30,0x84] @ CHECK-THUMB: mrs r4, sp_mon @ encoding: [0xed,0xf3,0x30,0x84]
@ CHECK-THUMB: mrs r6, SPSR_mon @ encoding: [0xfc,0xf3,0x30,0x86] @ CHECK-THUMB: mrs r6, SPSR_mon @ encoding: [0xfc,0xf3,0x30,0x86]
mrs r6, elr_hyp mrs r6, elr_hyp
mrs r8, sp_hyp mrs r8, sp_hyp
mrs r10, spsr_hyp mrs r10, spsr_hyp
@ CHECK-ARM: mrs r6, elr_hyp @ encoding: [0x00,0x63,0x2e,0xe1] @ CHECK-ARM: mrs r6, elr_hyp @ encoding: [0x00,0x63,0x0e,0xe1]
@ CHECK-ARM: mrs r8, sp_hyp @ encoding: [0x00,0x83,0x2f,0xe1] @ CHECK-ARM: mrs r8, sp_hyp @ encoding: [0x00,0x83,0x0f,0xe1]
@ CHECK-ARM: mrs r10, SPSR_hyp @ encoding: [0x00,0xa3,0x6e,0xe1] @ CHECK-ARM: mrs r10, SPSR_hyp @ encoding: [0x00,0xa3,0x4e,0xe1]
@ CHECK-THUMB: mrs r6, elr_hyp @ encoding: [0xee,0xf3,0x30,0x86] @ CHECK-THUMB: mrs r6, elr_hyp @ encoding: [0xee,0xf3,0x30,0x86]
@ CHECK-THUMB: mrs r8, sp_hyp @ encoding: [0xef,0xf3,0x30,0x88] @ CHECK-THUMB: mrs r8, sp_hyp @ encoding: [0xef,0xf3,0x30,0x88]
@ CHECK-THUMB: mrs r10, SPSR_hyp @ encoding: [0xfe,0xf3,0x30,0x8a] @ CHECK-THUMB: mrs r10, SPSR_hyp @ encoding: [0xfe,0xf3,0x30,0x8a]
msr r8_usr, r2 msr r8_usr, r2
msr r9_usr, r3 msr r9_usr, r3
msr r10_usr, r5 msr r10_usr, r5
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test/MC/Disassembler/ARM/move-banked-regs-arm.txt

@ RUN: llvm-mc -disassemble -triple armv7 -mcpu=cyclone %s | FileCheck %s @ RUN: llvm-mc -disassemble -triple armv7 -mcpu=cyclone %s | FileCheck %s
[0x00,0x22,0x20,0xe1] [0x00,0x22,0x00,0xe1]
[0x00,0x32,0x21,0xe1] [0x00,0x32,0x01,0xe1]
[0x00,0x52,0x22,0xe1] [0x00,0x52,0x02,0xe1]
[0x00,0x72,0x23,0xe1] [0x00,0x72,0x03,0xe1]
[0x00,0xb2,0x24,0xe1] [0x00,0xb2,0x04,0xe1]
[0x00,0x12,0x25,0xe1] [0x00,0x12,0x05,0xe1]
[0x00,0x22,0x26,0xe1] [0x00,0x22,0x06,0xe1]
@ CHECK: mrs r2, r8_usr @ CHECK: mrs r2, r8_usr
@ CHECK: mrs r3, r9_usr @ CHECK: mrs r3, r9_usr
@ CHECK: mrs r5, r10_usr @ CHECK: mrs r5, r10_usr
@ CHECK: mrs r7, r11_usr @ CHECK: mrs r7, r11_usr
@ CHECK: mrs r11, r12_usr @ CHECK: mrs r11, r12_usr
@ CHECK: mrs r1, sp_usr @ CHECK: mrs r1, sp_usr
@ CHECK: mrs r2, lr_usr @ CHECK: mrs r2, lr_usr
[0x00,0x22,0x28,0xe1] [0x00,0x22,0x08,0xe1]
[0x00,0x32,0x29,0xe1] [0x00,0x32,0x09,0xe1]
[0x00,0x52,0x2a,0xe1] [0x00,0x52,0x0a,0xe1]
[0x00,0x72,0x2b,0xe1] [0x00,0x72,0x0b,0xe1]
[0x00,0xb2,0x2c,0xe1] [0x00,0xb2,0x0c,0xe1]
[0x00,0x12,0x2d,0xe1] [0x00,0x12,0x0d,0xe1]
[0x00,0x22,0x2e,0xe1] [0x00,0x22,0x0e,0xe1]
[0x00,0x32,0x6e,0xe1] [0x00,0x32,0x4e,0xe1]
@ CHECK: mrs r2, r8_fiq @ CHECK: mrs r2, r8_fiq
@ CHECK: mrs r3, r9_fiq @ CHECK: mrs r3, r9_fiq
@ CHECK: mrs r5, r10_fiq @ CHECK: mrs r5, r10_fiq
@ CHECK: mrs r7, r11_fiq @ CHECK: mrs r7, r11_fiq
@ CHECK: mrs r11, r12_fiq @ CHECK: mrs r11, r12_fiq
@ CHECK: mrs r1, sp_fiq @ CHECK: mrs r1, sp_fiq
@ CHECK: mrs r2, lr_fiq @ CHECK: mrs r2, lr_fiq
@ CHECK: mrs r3, SPSR_fiq @ CHECK: mrs r3, SPSR_fiq
[0x00,0x43,0x20,0xe1] [0x00,0x43,0x00,0xe1]
[0x00,0x93,0x21,0xe1] [0x00,0x93,0x01,0xe1]
[0x00,0x13,0x60,0xe1] [0x00,0x13,0x40,0xe1]
@ CHECK: mrs r4, lr_irq @ CHECK: mrs r4, lr_irq
@ CHECK: mrs r9, sp_irq @ CHECK: mrs r9, sp_irq
@ CHECK: mrs r1, SPSR_irq @ CHECK: mrs r1, SPSR_irq
[0x00,0x13,0x22,0xe1] [0x00,0x13,0x02,0xe1]
[0x00,0x33,0x23,0xe1] [0x00,0x33,0x03,0xe1]
[0x00,0x53,0x62,0xe1] [0x00,0x53,0x42,0xe1]
@ CHECK: mrs r1, lr_svc @ CHECK: mrs r1, lr_svc
@ CHECK: mrs r3, sp_svc @ CHECK: mrs r3, sp_svc
@ CHECK: mrs r5, SPSR_svc @ CHECK: mrs r5, SPSR_svc
[0x00,0x53,0x24,0xe1] [0x00,0x53,0x04,0xe1]
[0x00,0x73,0x25,0xe1] [0x00,0x73,0x05,0xe1]
[0x00,0x93,0x64,0xe1] [0x00,0x93,0x44,0xe1]
@ CHECK: mrs r5, lr_abt @ CHECK: mrs r5, lr_abt
@ CHECK: mrs r7, sp_abt @ CHECK: mrs r7, sp_abt
@ CHECK: mrs r9, SPSR_abt @ CHECK: mrs r9, SPSR_abt
[0x00,0x93,0x26,0xe1] [0x00,0x93,0x06,0xe1]
[0x00,0xb3,0x27,0xe1] [0x00,0xb3,0x07,0xe1]
[0x00,0xc3,0x66,0xe1] [0x00,0xc3,0x46,0xe1]
@ CHECK: mrs r9, lr_und @ CHECK: mrs r9, lr_und
@ CHECK: mrs r11, sp_und @ CHECK: mrs r11, sp_und
@ CHECK: mrs r12, SPSR_und @ CHECK: mrs r12, SPSR_und
[0x00,0x23,0x2c,0xe1] [0x00,0x23,0x0c,0xe1]
[0x00,0x43,0x2d,0xe1] [0x00,0x43,0x0d,0xe1]
[0x00,0x63,0x6c,0xe1] [0x00,0x63,0x4c,0xe1]
@ CHECK: mrs r2, lr_mon @ CHECK: mrs r2, lr_mon
@ CHECK: mrs r4, sp_mon @ CHECK: mrs r4, sp_mon
@ CHECK: mrs r6, SPSR_mon @ CHECK: mrs r6, SPSR_mon
[0x00,0x63,0x2e,0xe1] [0x00,0x63,0x0e,0xe1]
[0x00,0x83,0x2f,0xe1] [0x00,0x83,0x0f,0xe1]
[0x00,0xa3,0x6e,0xe1] [0x00,0xa3,0x4e,0xe1]
@ CHECK: mrs r6, elr_hyp @ CHECK: mrs r6, elr_hyp
@ CHECK: mrs r8, sp_hyp @ CHECK: mrs r8, sp_hyp
@ CHECK: mrs r10, SPSR_hyp @ CHECK: mrs r10, SPSR_hyp
[0x02,0xf2,0x20,0xe1] [0x02,0xf2,0x20,0xe1]
[0x03,0xf2,0x21,0xe1] [0x03,0xf2,0x21,0xe1]
[0x05,0xf2,0x22,0xe1] [0x05,0xf2,0x22,0xe1]
[0x07,0xf2,0x23,0xe1] [0x07,0xf2,0x23,0xe1]
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