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[UBSan][MIPS] Adding support for MIPS64
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Authored by slthakur on Nov 19 2014, 4:42 AM.

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Summary

No MIPS64 architecture dependant code.
Patch dependant on http://reviews.llvm.org/D6402

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slthakur updated this revision to Diff 16375.Nov 19 2014, 4:42 AM
slthakur retitled this revision from to [UBSan][MIPS] Adding support for MIPS64.
slthakur updated this object.
slthakur edited the test plan for this revision. (Show Details)
slthakur added reviewers: kcc, rsmith, samsonov, petarj, dsanders.
slthakur set the repository for this revision to rL LLVM.
slthakur added subscribers: sdkie, Unknown Object (MLST), mohit.bhakkad and 2 others.
kcc edited edge metadata.Nov 19 2014, 12:55 PM

Maybe we should fix this in clang?

samsonov edited edge metadata.Nov 19 2014, 1:25 PM

+1. We should fix really fix this macro definition in Clang.

dsanders edited edge metadata.Nov 20 2014, 2:17 AM

Sagar has shown me the error he gets and (if it's as easy to fix as it looks) I'd rather fix the 'Cannot select ... i64,glue = addc ...' error by adding the necessary Pat's than remove the SIZEOF_INT128 macro.

In MipsInstrInfo.td there's this code to support 64-bit ints on MIPS32:

def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
               (SUBu GPR32:$lhs, GPR32:$rhs)>;
let AdditionalPredicates = [NotDSP] in {
   def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
                 (ADDu GPR32:$lhs, GPR32:$rhs)>;
   def : MipsPat<(addc  GPR32:$src, immSExt16:$imm),
                 (ADDiu GPR32:$src, imm:$imm)>;
}

We don't seem to have a GPR64 version of these three Pat's. I think it might be as simple as copying this into Mips64InstrInfo.td and changing the new copy from GPR32, ADD, and SUB, to GPR64, DADD, and DSUB respectively but I haven't had chance to try this change yet.

For the sake of completeness, the test case he showed me was:

int main ()
{
  __int128 a, b;
  a = 10;
  b = 20;
  a = a + b;
  return 0;
}

and the full error is:

fatal error: error in backend: Cannot select: 0x489e630: i64,glue = addc 0x489e510, 0x489bf98 [ORD=10] [ID=22]
    0x489e510: i64,ch = load 0x489cda8, 0x489cc88, 0x489c028<LD8[%a+8]> [ORD=8] [ID=20]
      0x489cc88: i64 = or 0x489c1d8, 0x489c9b8 [ORD=6] [ID=12]
        0x489c1d8: i64 = FrameIndex<1> [ID=4]
        0x489c9b8: i64 = Constant<8> [ID=10]
      0x489c028: i64 = undef [ID=3]
    0x489bf98: i64 = Constant<20> [ID=7]
slthakur updated this revision to Diff 16716.EditedNov 28 2014, 2:15 AM
slthakur updated this object.
slthakur edited edge metadata.
slthakur set the repository for this revision to rL LLVM.

Patch for removing SIZEOF_INT128 in clang has been submitted [1].
No MIPS64 architecture dependant code required for UBSan 64-bit

[1] http://reviews.llvm.org/D6402

samsonov accepted this revision.Nov 28 2014, 8:10 PM
samsonov edited edge metadata.

LGTM. Please submit if all test cases are really passing.

This revision is now accepted and ready to land.Nov 28 2014, 8:10 PM

Hi @samsonov,

Test case TypeCheck/misaligned.cpp uses a 48-bit address in one of its checks.
To make this test case pass for mips64 I need to use a 40-bit address.
Should I submit this change along with this patch or separately ?

Let's submit it in a separate change.

Hi @samsonov,

In TypeCheck/misaligned.cpp can I mark CHECK-WILD as expected failure for mips64 and misp64el just like arm has done?
Or is there any way to separate CHECK_WILD for mips64 architecture?

I don't think you can disable only CHECK-WILD under given architecture. So you'd have to either XFAIL the whole test, or factor CHECK-WILD part of it into a separate test case.

sdkie closed this revision.Dec 15 2014, 1:23 AM

closed by rL224239