This is an archive of the discontinued LLVM Phabricator instance.

[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".
ClosedPublic

Authored by ab on Nov 18 2014, 6:41 AM.

Details

Summary

r208210 introduced an optimization that improves the vector select
codegen by doing the setcc on vectors directly.
This is a problem when the setcc operands are i1s, because the
optimization would create vectors of i1, which aren't legal.

Part of PR21549.

Diff Detail

Repository
rL LLVM

Event Timeline

ab updated this revision to Diff 16332.Nov 18 2014, 6:41 AM
ab retitled this revision from to [AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR"..
ab updated this object.
ab edited the test plan for this revision. (Show Details)
ab added a reviewer: t.p.northover.
ab added a subscriber: Unknown Object (MLST).
ab added a comment.Dec 1 2014, 11:42 AM

Ping for a short patch!

-Ahmed

t.p.northover accepted this revision.Dec 1 2014, 12:32 PM
t.p.northover edited edge metadata.

Sorry Ahmed, I think this looks fine.

Tim.

This revision is now accepted and ready to land.Dec 1 2014, 12:32 PM
ab closed this revision.Dec 1 2014, 12:59 PM
ab updated this revision to Diff 16783.

Closed by commit rL223075 (authored by @ab).