Add VSX loads/stores to fastisel for PPC target

[seurer]

Summary

This patch adds VSX floating point loads and stores to fastisel.

Along with the change to tablegen (D6220), VSX instructions are now fully supported in fastisel.

[echristo]

Few nits:

Clang-format? :)

Periods at the end of sentences.

Couple of inline comments.

Thanks!

/home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp

143

I'd prefer to pull the Register != 0 out of this so that we can keep the general pattern of checking it. Thoughts?

492

Hmm.. explain the assert here?

[wschmidt]

Looks pretty good -- just a couple of inline comments.

/home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp

145

I'd like to see this named isVSFRCRegister or the like. The VSFRC class comprises only the most-significant-half of each of the VSX registers (the VSRs), so I feel the name is misleading.

492

Yeah, I don't get this either.

[seurer]

/home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp

143

If the register is 0 then the call to getRegClass will fail in an assertion. Or rather, another function it calls will fail.

145

OK, done.

[seurer]

/home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp

492

Early on when I was experimenting with this the base reg was sometimes 0 which caused code further on to fail. It is no longer necessary and I will remove it.

[echristo]

/home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp

143

Sure. Make it an assert rather than a check? Should be checking that ResultReg isn't equal to 0 earlier I think.

[seurer]

Updated with changes to address comments.

Note: the check for ResultReg != 0 for the load case is really necessary.

[hfinkel]

You have formatting to fix, otherwise LGTM.

In case you did not know, you can run clang-format directly on your patch file.

/home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp

489

Comma after 0.

490

Extra space before 'be'

491

No space after isVSFRCRegister.

506

Add spaces around ==.

520

Add spaces around ==.

622

Comma after 0.

623

Extra space before 'be'.

636

Add spaces around ==.

653

Add spaces around ==.

[seurer]

Code checked in [llvm] r223507

/home/seurer/llvm/llvm-oneoff/lib/Target/PowerPC/PPCFastISel.cpp

private:
     bool SelectRet(const Instruction *I);
     bool SelectTrunc(const Instruction *I);
     bool SelectIntExt(const Instruction *I);
 
   // Utility routines.
   private:
     bool isTypeLegal(Type *Ty, MVT &VT);
     bool isLoadTypeLegal(Type *Ty, MVT &VT);
+    bool isVSFRCRegister (unsigned Register) const {
+      return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
+    }
     bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
                     bool isZExt, unsigned DestReg);
     bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
                      const TargetRegisterClass *RC, bool IsZExt = true,
                      unsigned FP64LoadOpc = PPC::LFD);
     bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
     bool PPCComputeAddress(const Value *Obj, Address &Addr);
     void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
                             unsigned &IndexReg);
case MVT::f64:
       Opc = FP64LoadOpc;
       break;
   }
 
   // If necessary, materialize the offset into a register and use
   // the indexed form.  Also handle stack pointers with special needs.
   unsigned IndexReg = 0;
   PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
+
+  // If this is a potential VSX load with an offset of 0 a VSX indexed load can
+  //  be used.
+  bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister (ResultReg);
+  if (IsVSFRC && (Opc == PPC::LFD) && 
+      (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
+      (Addr.Offset == 0)) {
+    UseOffset = false;
+  }
+
   if (ResultReg == 0)
     ResultReg = createResultReg(UseRC);
 
   // Note: If we still have a frame index here, we know the offset is
   // in range, as otherwise PPCSimplifyAddress would have converted it
   // into a RegBase.
   if (Addr.BaseType == Address::FrameIndexBase) {
+     // VSX only provides an indexed load.
+    if (IsVSFRC && Opc==PPC::LFD) return false;
 
     MachineMemOperand *MMO =
       FuncInfo.MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
         MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
         MFI.getObjectAlignment(Addr.Base.FI));
 
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
       .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
 
   // Base reg with offset in range.
   } else if (UseOffset) {
+     // VSX only provides an indexed load.
+    if (IsVSFRC && Opc==PPC::LFD) return false;
 
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
       .addImm(Addr.Offset).addReg(Addr.Base.Reg);
 
   // Indexed form.
   } else {
     // Get the RR opcode corresponding to the RI one.  FIXME: It would be
     // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
     // is hard to get at.
     switch (Opc) {
       default:        llvm_unreachable("Unexpected opcode!");
       case PPC::LBZ:    Opc = PPC::LBZX;    break;
       case PPC::LBZ8:   Opc = PPC::LBZX8;   break;
       case PPC::LHZ:    Opc = PPC::LHZX;    break;
       case PPC::LHZ8:   Opc = PPC::LHZX8;   break;
       case PPC::LHA:    Opc = PPC::LHAX;    break;
       case PPC::LHA8:   Opc = PPC::LHAX8;   break;
       case PPC::LWZ:    Opc = PPC::LWZX;    break;
       case PPC::LWZ8:   Opc = PPC::LWZX8;   break;
       case PPC::LWA:    Opc = PPC::LWAX;    break;
       case PPC::LWA_32: Opc = PPC::LWAX_32; break;
       case PPC::LD:     Opc = PPC::LDX;     break;
       case PPC::LFS:    Opc = PPC::LFSX;    break;
-      case PPC::LFD:    Opc = PPC::LFDX;    break;
+      case PPC::LFD:    Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
     }
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
       .addReg(Addr.Base.Reg).addReg(IndexReg);
   }
 
   return true;
 }
 
case MVT::f64:
       break;
   }
 
   // If necessary, materialize the offset into a register and use
   // the indexed form.  Also handle stack pointers with special needs.
   unsigned IndexReg = 0;
   PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
 
+  // If this is a potential VSX store with an offset of 0 a VSX indexed store
+  //  can be used.
+  bool IsVSFRC = isVSFRCRegister (SrcReg);
+  if (IsVSFRC && (Opc == PPC::STFD) && 
+      (Addr.BaseType != Address::FrameIndexBase) && UseOffset && 
+      (Addr.Offset == 0)) {
+    UseOffset = false;
+  }
+
   // Note: If we still have a frame index here, we know the offset is
   // in range, as otherwise PPCSimplifyAddress would have converted it
   // into a RegBase.
   if (Addr.BaseType == Address::FrameIndexBase) {
+     // VSX only provides an indexed store.
+    if (IsVSFRC && Opc==PPC::STFD) return false;
+
     MachineMemOperand *MMO =
       FuncInfo.MF->getMachineMemOperand(
         MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
         MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
         MFI.getObjectAlignment(Addr.Base.FI));
 
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
         .addReg(SrcReg)
         .addImm(Addr.Offset)
         .addFrameIndex(Addr.Base.FI)
         .addMemOperand(MMO);
 
   // Base reg with offset in range.
-  } else if (UseOffset)
+  } else if (UseOffset) {
+     // VSX only provides an indexed store.
+    if (IsVSFRC && Opc==PPC::STFD) return false;
+    
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
       .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
 
   // Indexed form.
-  else {
+  } else {
     // Get the RR opcode corresponding to the RI one.  FIXME: It would be
     // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
     // is hard to get at.
     switch (Opc) {
       default:        llvm_unreachable("Unexpected opcode!");
       case PPC::STB:  Opc = PPC::STBX;  break;
       case PPC::STH : Opc = PPC::STHX;  break;
       case PPC::STW : Opc = PPC::STWX;  break;
       case PPC::STB8: Opc = PPC::STBX8; break;
       case PPC::STH8: Opc = PPC::STHX8; break;
       case PPC::STW8: Opc = PPC::STWX8; break;
       case PPC::STD:  Opc = PPC::STDX;  break;
       case PPC::STFS: Opc = PPC::STFSX; break;
-      case PPC::STFD: Opc = PPC::STFDX; break;
+      case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
     }
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
       .addReg(SrcReg).addReg(Addr.Base.Reg).addReg(IndexReg);
   }
 
   return true;
 }