[AArch64] Keep flags on the condition when instantiating a CB branch.

[ab]

Summary

Reversing a CB* instruction used to drop the flags on the condition. On the included testcase, this lead to a read from an undefined vreg.
Using addOperand keeps the flags.

Also, I'm not sure it's a good thing that the idiom:

BuildMI(...).addReg(MO->getReg())

is preferred to:

BuildMI(...).addOperand(MO)

Here this actually makes a difference, I'm wondering if there are other places where the difference is more important than some missing undef.

[t.p.northover]

Interesting point on the general principle; I'll have to bear it in mind in future. A common case is expanding a single instruction to multiple ones, where you often need to use different flags on the same register throughout the process.

Either way, this patch looks obvious. Go for it!

Tim.

[ab]

Closed by commit rL221507 (authored by @ab).

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

 void AArch64InstrInfo::instantiateCondBranch(
     MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
     const SmallVectorImpl<MachineOperand> &Cond) const {
   if (Cond[0].getImm() != -1) {
     // Regular Bcc
     BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
   } else {
     // Folded compare-and-branch
+    // Note that we use addOperand instead of addReg to keep the flags.
     const MachineInstrBuilder MIB =
-        BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());
+        BuildMI(&MBB, DL, get(Cond[1].getImm())).addOperand(Cond[2]);
     if (Cond.size() > 3)
       MIB.addImm(Cond[3].getImm());
     MIB.addMBB(TBB);
   }
 }
 
 unsigned AArch64InstrInfo::InsertBranch(
     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,

llvm/trunk/test/CodeGen/AArch64/br-undef-cond.ll

+; RUN: llc < %s -verify-machineinstrs
+
+; Make sure we don't end up with a CBNZ of an undef v-/phys-reg.
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios"
+
+declare void @bar(i8*)
+
+define void @foo(i8* %m, i32 %off0) {
+.thread1653:
+  br i1 undef, label %0, label %.thread1880
+
+  %1 = icmp eq i32 undef, 0
+  %.not = xor i1 %1, true
+  %brmerge = or i1 %.not, undef
+  br i1 %brmerge, label %.thread1880, label %.thread1705
+
+.thread1705:
+  ret void
+
+.thread1880:
+  %m1652.ph = phi i8* [ %m, %0 ], [ null, %.thread1653 ]
+  call void @bar(i8* %m1652.ph)
+  ret void
+}