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[mips] Enable code generation for the MIPS II target.
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Authored by vkalintiris on Nov 6 2014, 8:51 AM.

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Summary

This patch enables code generation for the MIPS II target. Pre-Mips32
targets don't have the MUL instruction, so we add the correspondent
pattern that uses the MULT/MFLO combination in order to retrieve the
product.

This is WIP as we don't support code generation for select nodes due to
the lack of conditional-move instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

vkalintiris updated this revision to Diff 15877.Nov 6 2014, 8:51 AM
vkalintiris retitled this revision from to [mips] Enable code generation for the MIPS II target..
vkalintiris updated this object.
vkalintiris edited the test plan for this revision. (Show Details)
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Nov 10 2014, 6:30 AM
dsanders edited edge metadata.

LGTM with some test corrections and a nit. Also, please reword the title line of the commit message. At the moment it implies that MIPS-II will work after that patch and that isn't quite true yet.

I understand you're testing with a qemu that has been patched to have a MIPS-II CPU definition. Are you planning to upstream that patch to qemu.org?

lib/Target/Mips/MipsSubtarget.cpp
132–134 ↗(On Diff #15877)

Nit: Line wrapping

test/CodeGen/Mips/llvm-ir/mul.ll
101 ↗(On Diff #15877)

This result register isn't guaranteed to be $2. It ought to be checked with a variable.

105 ↗(On Diff #15877)

This result register isn't guaranteed to be $2. It ought to be checked with a variable.

111–112 ↗(On Diff #15877)

These result registers aren't guaranteed to be $2 and $4 respectively. They ought to be checked with a variable.

117 ↗(On Diff #15877)

This result register isn't guaranteed to be $2. It ought to be checked with a variable.

119 ↗(On Diff #15877)

This result register isn't guaranteed to be $2. It ought to be checked with a variable.

This revision is now accepted and ready to land.Nov 10 2014, 6:30 AM
In D6150#4, @dsanders wrote:

I understand you're testing with a qemu that has been patched to have a MIPS-II CPU definition. Are you planning to upstream that patch to qemu.org?

Hi Daniel, you are right. There wasn't any real CPU model for MIPS-II in Qemu so I added one based on the existing definition of the mips32r5-generic CPU.
I will send the patch for review to qemu sometime during this week.

vkalintiris closed this revision.Nov 11 2014, 3:35 AM
vkalintiris updated this revision to Diff 16036.

Closed by commit rL221686 (authored by @vkalintiris).