[mips] Remove MipsCC::analyzeCallOperands in favour of CCState::AnalyzeCallOperands. NFC

[dsanders]

Summary

In addition to the usual f128 workaround, it was also necessary to provide
a means of accessing ArgListEntry::IsFixed.

[dsanders]

Added David as reviewer

[vmedic]

LGTM

include/llvm/Target/TargetCallingConv.td

 /// CCIfSplit - If this argument is marked with the 'split' attribute, apply
 /// the specified action.
 class CCIfSplit<CCAction A> : CCIf<"ArgFlags.isSplit()", A> {}
 
 /// CCIfSRet - If this argument is marked with the 'sret' attribute, apply
 /// the specified action.
 class CCIfSRet<CCAction A> : CCIf<"ArgFlags.isSRet()", A> {}
 
+/// CCIfVarArg - If the current function is vararg - apply the action
+class CCIfVarArg<CCAction A> : CCIf<"State.isVarArg()", A> {}
+
 /// CCIfNotVarArg - If the current function is not vararg - apply the action
 class CCIfNotVarArg<CCAction A> : CCIf<"!State.isVarArg()", A> {}
 
 /// CCAssignToReg - This action matches if there is a register in the specified
 /// list that is still available.  If so, it assigns the value to the first
 /// available register and succeeds.
 class CCAssignToReg<list<Register> regList> : CCAction {
   list<Register> RegList = regList;

lib/Target/Mips/MipsCallingConv.td

def CC_Mips_VarArg : CallingConv<[
   CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>,
 
   // FIXME: There wasn't an EABI case in the original code and it seems unlikely
   //        that it's the same as CC_MipsN_VarArg
   CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>,
   CCDelegateTo<CC_MipsN_VarArg>
 ]>;
 
+def CC_Mips : CallingConv<[
+  CCIfVarArg<
+      CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)",
+          CCDelegateTo<CC_Mips_VarArg>>>,
+  CCDelegateTo<CC_Mips_FixedArg>
+]>;
+
 //===----------------------------------------------------------------------===//
 // Callee-saved register lists.
 //===----------------------------------------------------------------------===//
 
 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
                                                (sequence "S%u", 7, 0))>;
 
 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,

lib/Target/Mips/MipsISelLowering.h

protected:
 
     /// MipsCC - This class provides methods used to analyze formal and call
     /// arguments and inquire about calling convention information.
     class MipsCC {
     public:
       MipsCC(CallingConv::ID CallConv, const MipsSubtarget &Subtarget,
              CCState &Info);
 
-      void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
-                               std::vector<ArgListEntry> &FuncArgs,
-                               CCState &State);
-
       /// reservedArgArea - The size of the area the caller reserves for
       /// register arguments. This is 16-byte if ABI is O32.
       unsigned reservedArgArea() const;
 
       /// Return pointer to array of integer argument registers.
       const ArrayRef<MCPhysReg> intArgRegs() const;
 
     private:

lib/Target/Mips/MipsISelLowering.cpp

void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs) {
     const MachineFunction &MF = getMachineFunction();
     for (unsigned i = 0; i < Outs.size(); ++i)
       OriginalArgWasF128.push_back(
           originalTypeIsF128(MF.getFunction()->getReturnType(), nullptr));
   }
 
   /// Identify lowered values that originated from f128 arguments and record
   /// this.
-  void PreAnalyzeCallOperandsForF128(
+  void PreAnalyzeCallOperands(
       const SmallVectorImpl<ISD::OutputArg> &Outs,
-      std::vector<TargetLowering::ArgListEntry> &FuncArgs, SDNode *CallNode) {
-    for (unsigned i = 0; i < Outs.size(); ++i)
+      std::vector<TargetLowering::ArgListEntry> &FuncArgs,
+      const SDNode *CallNode) {
+    for (unsigned i = 0; i < Outs.size(); ++i) {
       OriginalArgWasF128.push_back(
           originalTypeIsF128(FuncArgs[Outs[i].OrigArgIndex].Ty, CallNode));
+      CallOperandIsFixed.push_back(Outs[i].IsFixed);
+    }
   }
 
   /// Identify lowered values that originated from f128 arguments and record
   /// this.
   void
   PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins) {
     const MachineFunction &MF = getMachineFunction();
     for (unsigned i = 0; i < Ins.size(); ++i) {
for (unsigned i = 0; i < Ins.size(); ++i) {
       OriginalArgWasF128.push_back(
           originalTypeIsF128(FuncArg->getType(), nullptr));
     }
   }
 
   /// Records whether the value has been lowered from an f128.
   SmallVector<bool, 4> OriginalArgWasF128;
 
+  /// Records whether the value was a fixed argument.
+  /// See ISD::OutputArg::IsFixed,
+  SmallVector<bool, 4> CallOperandIsFixed;
+
   // Used to handle MIPS16-specific calling convention tweaks.
   // FIXME: This should probably be a fully fledged calling convention.
   SpecialCallingConvType SpecialCallingConv;
 
 public:
-  // FIXME: Remove this from a public inteface ASAP. It's a temporary trap door
-  //        to allow analyzeCallOperands to be removed incrementally.
-  void PreAnalyzeCallOperandsForF128_(
-      const SmallVectorImpl<ISD::OutputArg> &Outs,
-      std::vector<TargetLowering::ArgListEntry> &FuncArgs, SDNode *CallNode) {
-    PreAnalyzeCallOperandsForF128(Outs, FuncArgs, CallNode);
-  }
-  // FIXME: Remove this from a public inteface ASAP. It's a temporary trap door
-  //        to clean up after the above functions.
-  void ClearOriginalArgWasF128() { OriginalArgWasF128.clear(); }
 
   MipsCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
               SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
               SpecialCallingConvType SpecialCC = NoSpecialCallingConv)
       : CCState(CC, isVarArg, MF, locs, C), SpecialCallingConv(SpecialCC) {}
 
+  void
+  AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      CCAssignFn Fn,
+                      std::vector<TargetLowering::ArgListEntry> &FuncArgs,
+                      const SDNode *CallNode) {
+    PreAnalyzeCallOperands(Outs, FuncArgs, CallNode);
+    CCState::AnalyzeCallOperands(Outs, Fn);
+    OriginalArgWasF128.clear();
+    CallOperandIsFixed.clear();
+  }
+
+  // The AnalyzeCallOperands in the base class is not usable since we must
+  // provide a means of accessing ArgListEntry::IsFixed. Delete them from this
+  // class. This doesn't stop them being used via the base class though.
+  void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
+                           CCAssignFn Fn) = delete;
+  void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
+                           SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
+                           CCAssignFn Fn) = delete;
+
   void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
                               CCAssignFn Fn) {
     PreAnalyzeFormalArgumentsForF128(Ins);
     CCState::AnalyzeFormalArguments(Ins, Fn);
     OriginalArgWasF128.clear();
   }
 
   void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
                    CCAssignFn Fn) {
     PreAnalyzeReturnForF128(ArgsFlags);
     bool Return = CCState::CheckReturn(ArgsFlags, Fn);
     OriginalArgWasF128.clear();
     return Return;
   }
 
   bool WasOriginalArgF128(unsigned ValNo) { return OriginalArgWasF128[ValNo]; }
+  bool IsCallOperandFixed(unsigned ValNo) { return CallOperandIsFixed[ValNo]; }
   SpecialCallingConvType getSpecialCallingConv() { return SpecialCallingConv; }
 };
 }
 
 // If I is a shifted mask, set the size (Size) and the first bit of the
 // mask (Pos), and return true.
 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
 
   // Analyze operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   MipsCCState CCInfo(
       CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
       MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
   MipsCC MipsCCInfo(CallConv, Subtarget, CCInfo);
 
-  CCInfo.PreAnalyzeCallOperandsForF128_(Outs, CLI.getArgs(), Callee.getNode());
-  MipsCCInfo.analyzeCallOperands(Outs, CLI.getArgs(), CCInfo);
-  CCInfo.ClearOriginalArgWasF128();
+  CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
 
   // Get a count of how many bytes are to be pushed on the stack.
   unsigned NextStackOffset = CCInfo.getNextStackOffset();
 
   // Check if it's really possible to do a tail call.
   if (IsTailCall)
     IsTailCall = isEligibleForTailCallOptimization(
         CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());

 MipsTargetLowering::MipsCC::MipsCC(CallingConv::ID CC,
                                    const MipsSubtarget &Subtarget_,
                                    CCState &Info)
     : CallConv(CC), Subtarget(Subtarget_) {
   // Pre-allocate reserved argument area.
   Info.AllocateStack(reservedArgArea(), 1);
 }
 
-void MipsTargetLowering::MipsCC::analyzeCallOperands(
-    const SmallVectorImpl<ISD::OutputArg> &Args,
-    std::vector<ArgListEntry> &FuncArgs, CCState &State) {
-  assert((CallConv != CallingConv::Fast || !State.isVarArg()) &&
-         "CallingConv::Fast shouldn't be used for vararg functions.");
-
-  unsigned NumOpnds = Args.size();
-
-  for (unsigned I = 0; I != NumOpnds; ++I) {
-    MVT ArgVT = Args[I].VT;
-    ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
-    bool R;
-
-    if (State.isVarArg() && !Args[I].IsFixed)
-      R = CC_Mips_VarArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
-    else
-      R = CC_Mips_FixedArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, State);
-
-    if (R) {
-#ifndef NDEBUG
-      dbgs() << "Call operand #" << I << " has unhandled type "
-             << EVT(ArgVT).getEVTString();
-#endif
-      llvm_unreachable(nullptr);
-    }
-  }
-}
-
 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
   return (Subtarget.isABI_O32() && (CallConv != CallingConv::Fast)) ? 16 : 0;
 }
 
 const ArrayRef<MCPhysReg> MipsTargetLowering::MipsCC::intArgRegs() const {
   if (Subtarget.isABI_O32())
     return makeArrayRef(O32IntRegs);
   return makeArrayRef(Mips64IntRegs);