This is an archive of the discontinued LLVM Phabricator instance.

Differential D5900

R600/SI: Match integer min / max instructions
ClosedPublic

Authored by arsenm on Oct 21 2014, 5:37 PM.

Details

Reviewers
arsenm

Diff Detail

Event Timeline

arsenm updated this revision to Diff 15227.Oct 21 2014, 5:37 PM
arsenm retitled this revision from to R600/SI: Match integer min / max instructions .
arsenm updated this object.
arsenm edited the test plan for this revision. (Show Details)
arsenm added a subscriber: Unknown Object (MLST).
arsenm added a comment.Nov 3 2014, 2:53 PM

ping

arsenm added a comment.Nov 11 2014, 3:18 PM

ping

arsenm added a comment.Nov 13 2014, 1:43 PM

ping

arsenm accepted this revision.Nov 14 2014, 10:30 AM
arsenm added a reviewer: arsenm.

r222015

This revision is now accepted and ready to land.Nov 14 2014, 10:30 AM
arsenm closed this revision.Nov 14 2014, 10:30 AM

Revision Contents

PathSize
lib/
Target/
R600/
25 lines
90 lines
test/
CodeGen/
R600/
99 lines
99 lines

Diff 15227

lib/Target/R600/AMDGPUISelLowering.h

Show First 20 Lines • Show All 134 Lines • ▼ Show 20 Linespublic:
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
void ReplaceNodeResults(SDNode * N, void ReplaceNodeResults(SDNode * N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
SDValue CombineMinMax(SDLoc DL, SDValue CombineFMinMax(SDLoc DL,
EVT VT, EVT VT,
SDValue LHS, SDValue LHS,
SDValue RHS, SDValue RHS,
SDValue True, SDValue True,
SDValue False, SDValue False,
SDValue CC, SDValue CC,
SelectionDAG &DAG) const; SelectionDAG &DAG) const;
SDValue CombineIMinMax(SDLoc DL,
EVT VT,
SDValue LHS,
SDValue RHS,
SDValue True,
SDValue False,
SDValue CC,
SelectionDAG &DAG) const;
const char* getTargetNodeName(unsigned Opcode) const override; const char* getTargetNodeName(unsigned Opcode) const override;
virtual SDNode *PostISelFolding(MachineSDNode *N, virtual SDNode *PostISelFolding(MachineSDNode *N,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
return N; return N;
} }
/// \brief Determine which of the bits specified in \p Mask are known to be /// \brief Determine which of the bits specified in \p Mask are known to be
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

lib/Target/R600/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 975 Lines • ▼ Show 20 LinesSDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA, SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
Op.getOperand(3)); Op.getOperand(3));
return DAG.getNode(ISD::FADD, DL, VT, return DAG.getNode(ISD::FADD, DL, VT,
DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)), DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
OneSubAC); OneSubAC);
} }
/// \brief Generate Min/Max node /// \brief Generate Min/Max node
SDValue AMDGPUTargetLowering::CombineMinMax(SDLoc DL, SDValue AMDGPUTargetLowering::CombineFMinMax(SDLoc DL,
EVT VT, EVT VT,
SDValue LHS, SDValue LHS,
SDValue RHS, SDValue RHS,
SDValue True, SDValue True,
SDValue False, SDValue False,
SDValue CC, SDValue CC,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
if (VT != MVT::f32 &&
(VT != MVT::f64 ||
Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS))
return SDValue();
if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True)) if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
return SDValue(); return SDValue();
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
switch (CCOpcode) { switch (CCOpcode) {
case ISD::SETOEQ: case ISD::SETOEQ:
case ISD::SETONE: case ISD::SETONE:
case ISD::SETUNE: case ISD::SETUNE:
Show All 28 Lines case ISD::SETOGT: {
return DAG.getNode(Opc, DL, VT, LHS, RHS); return DAG.getNode(Opc, DL, VT, LHS, RHS);
} }
case ISD::SETCC_INVALID: case ISD::SETCC_INVALID:
llvm_unreachable("Invalid setcc condcode!"); llvm_unreachable("Invalid setcc condcode!");
} }
return SDValue(); return SDValue();
} }
/// \brief Generate Min/Max node
SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
EVT VT,
SDValue LHS,
SDValue RHS,
SDValue True,
SDValue False,
SDValue CC,
SelectionDAG &DAG) const {
if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
return SDValue();
ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
switch (CCOpcode) {
case ISD::SETULE:
case ISD::SETULT: {
unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
return DAG.getNode(Opc, DL, VT, LHS, RHS);
}
case ISD::SETLE:
case ISD::SETLT: {
unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
return DAG.getNode(Opc, DL, VT, LHS, RHS);
}
case ISD::SETGT:
case ISD::SETGE: {
unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
return DAG.getNode(Opc, DL, VT, LHS, RHS);
}
case ISD::SETUGE:
case ISD::SETUGT: {
unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
return DAG.getNode(Opc, DL, VT, LHS, RHS);
}
default:
return SDValue();
}
}
SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op, SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
LoadSDNode *Load = cast<LoadSDNode>(Op); LoadSDNode *Load = cast<LoadSDNode>(Op);
EVT MemVT = Load->getMemoryVT(); EVT MemVT = Load->getMemoryVT();
EVT MemEltVT = MemVT.getVectorElementType(); EVT MemEltVT = MemVT.getVectorElementType();
EVT LoadVT = Op.getValueType(); EVT LoadVT = Op.getValueType();
EVT EltVT = LoadVT.getVectorElementType(); EVT EltVT = LoadVT.getVectorElementType();
▲ Show 20 Lines • Show All 1,044 Lines • ▼ Show 20 Lines case AMDGPUISD::MUL_U24: {
simplifyI24(N0, DCI); simplifyI24(N0, DCI);
simplifyI24(N1, DCI); simplifyI24(N1, DCI);
return SDValue(); return SDValue();
} }
case ISD::SELECT_CC: { case ISD::SELECT_CC: {
SDLoc DL(N); SDLoc DL(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
if (VT == MVT::f32 ||
(VT == MVT::f64 &&
Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)) {
SDValue LHS = N->getOperand(0); SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1); SDValue RHS = N->getOperand(1);
SDValue True = N->getOperand(2); SDValue True = N->getOperand(2);
SDValue False = N->getOperand(3); SDValue False = N->getOperand(3);
SDValue CC = N->getOperand(4); SDValue CC = N->getOperand(4);
return CombineMinMax(DL, VT, LHS, RHS, True, False, CC, DAG); return CombineFMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
}
break;
} }
case ISD::SELECT: { case ISD::SELECT: {
SDValue Cond = N->getOperand(0); SDValue Cond = N->getOperand(0);
if (Cond.getOpcode() == ISD::SETCC) { if (Cond.getOpcode() == ISD::SETCC) {
SDLoc DL(N); SDLoc DL(N);
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDValue LHS = Cond.getOperand(0); SDValue LHS = Cond.getOperand(0);
SDValue RHS = Cond.getOperand(1); SDValue RHS = Cond.getOperand(1);
SDValue CC = Cond.getOperand(2); SDValue CC = Cond.getOperand(2);
SDValue True = N->getOperand(1); SDValue True = N->getOperand(1);
SDValue False = N->getOperand(2); SDValue False = N->getOperand(2);
if (VT == MVT::f32 ||
(VT == MVT::f64 &&
Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)) {
return CombineFMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
}
return CombineMinMax(DL, VT, LHS, RHS, True, False, CC, DAG); // TODO: Implement min / max Evergreen instructions.
if (VT == MVT::i32 &&
Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
}
} }
break; break;
} }
case AMDGPUISD::BFE_I32: case AMDGPUISD::BFE_I32:
case AMDGPUISD::BFE_U32: { case AMDGPUISD::BFE_U32: {
assert(!N->getValueType(0).isVector() && assert(!N->getValueType(0).isVector() &&
"Vector handling of BFE not implemented"); "Vector handling of BFE not implemented");
▲ Show 20 Lines • Show All 320 Lines • Show Last 20 Lines

test/CodeGen/R600/max.ll

  • This file was added.
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
; FUNC-LABEL: @v_test_imax_sge_i32
; SI: V_MAX_I32_e32
define void @v_test_imax_sge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp sge i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_imax_sge_i32
; SI: S_MAX_I32
define void @s_test_imax_sge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp sge i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: @v_test_imax_sgt_i32
; SI: V_MAX_I32_e32
define void @v_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp sgt i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_imax_sgt_i32
; SI: S_MAX_I32
define void @s_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp sgt i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: @v_test_umax_uge_i32
; SI: V_MAX_U32_e32
define void @v_test_umax_uge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp uge i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_umax_uge_i32
; SI: S_MAX_U32
define void @s_test_umax_uge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp uge i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: @v_test_umax_ugt_i32
; SI: V_MAX_U32_e32
define void @v_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp ugt i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_umax_ugt_i32
; SI: S_MAX_U32
define void @s_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp ugt i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}

test/CodeGen/R600/min.ll

  • This file was added.
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare i32 @llvm.r600.read.tidig.x() nounwind readnone
; FUNC-LABEL: @v_test_imin_sle_i32
; SI: V_MIN_I32_e32
define void @v_test_imin_sle_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp sle i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_imin_sle_i32
; SI: S_MIN_I32
define void @s_test_imin_sle_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp sle i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: @v_test_imin_slt_i32
; SI: V_MIN_I32_e32
define void @v_test_imin_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp slt i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_imin_slt_i32
; SI: S_MIN_I32
define void @s_test_imin_slt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp slt i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: @v_test_umin_ule_i32
; SI: V_MIN_U32_e32
define void @v_test_umin_ule_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp ule i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_umin_ule_i32
; SI: S_MIN_U32
define void @s_test_umin_ule_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp ule i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: @v_test_umin_ult_i32
; SI: V_MIN_U32_e32
define void @v_test_umin_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
%gep0 = getelementptr i32 addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr i32 addrspace(1)* %bptr, i32 %tid
%outgep = getelementptr i32 addrspace(1)* %out, i32 %tid
%a = load i32 addrspace(1)* %gep0, align 4
%b = load i32 addrspace(1)* %gep1, align 4
%cmp = icmp ult i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %outgep, align 4
ret void
}
; FUNC-LABEL: @s_test_umin_ult_i32
; SI: S_MIN_U32
define void @s_test_umin_ult_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
%cmp = icmp ult i32 %a, %b
%val = select i1 %cmp, i32 %a, i32 %b
store i32 %val, i32 addrspace(1)* %out, align 4
ret void
}