[asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an index register.

[ygorshenin]

Summary

Fixed memory accesses with rbp as a base or an index register.

[eugenis]

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

30

why do you need cassert? This file has used assertions before.

137

Can LocalFrameReg be part of RegisterContext?

344

Maybe RegisterContext::addBusyReg() accepting a register or an X86Operand, and then choose the frame register in InstrumentMemOperandPrologue?

test/Instrumentation/AddressSanitizer/X86/asm_cfi.s

27

Hm, why is this test so complex? There are 4 memory accesses here => we emit prologue/epilogue 4 times, and it's not obvious which one is tested. Can you make it simpler? It looks like this test covers the new code, but I'm not 100% sure.

[ygorshenin]

Fixes.

[ygorshenin]

PTAL

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

30

And it uses them now. So, I thought, it's a right thing to include explicitly <cassert> and do not depend on an implicit inclusion.

137

Good point, thanks!

344

Good point, thanks!

test/Instrumentation/AddressSanitizer/X86/asm_cfi.s

27

Done.

[eugenis]

LGTM w/ nits

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

74

I think these should start with a capital letter.

79

I'd prefer named constants (or an enum) instead of magic index constants 0, 1, 2.

92

This may add NoRegister to BusyRegs, better avoid it.

[ygorshenin]

Fixes.

[ygorshenin]

Many thanks!

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

74

Done.

79

Done.

92

Done.

[ygorshenin]

Closed by commit rL220283 (authored by @ygorshenin).

lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp

 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCTargetAsmParser.h"
 #include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/CommandLine.h"
 #include <algorithm>
+#include <cassert>
+#include <vector>
 
 namespace llvm {
 namespace {
 
 static cl::opt<bool> ClAsanInstrumentAssembly(
     "asan-instrument-assembly",
     cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
     cl::init(false));

 std::string FuncName(unsigned AccessSize, bool IsWrite) {
   return std::string("__asan_report_") + (IsWrite ? "store" : "load") +
          utostr(AccessSize);
 }
 
 class X86AddressSanitizer : public X86AsmInstrumentation {
 public:
   struct RegisterContext {
+  public:
     RegisterContext(unsigned AddressReg, unsigned ShadowReg,
-                    unsigned ScratchReg)
-        : AddressReg(AddressReg), ShadowReg(ShadowReg), ScratchReg(ScratchReg) {
+                    unsigned ScratchReg) {
+      for (unsigned Reg : { AddressReg, ShadowReg, ScratchReg }) {
+        BusyRegs.push_back(convReg(Reg, MVT::i64));
+      }
     }
 
     unsigned addressReg(MVT::SimpleValueType VT) const {
-      return getX86SubSuperRegister(AddressReg, VT);
+      return convReg(BusyRegs[0], VT);
     }
 
     unsigned shadowReg(MVT::SimpleValueType VT) const {
-      return getX86SubSuperRegister(ShadowReg, VT);
+      return convReg(BusyRegs[1], VT);
     }
 
     unsigned scratchReg(MVT::SimpleValueType VT) const {
-      return getX86SubSuperRegister(ScratchReg, VT);
+      return convReg(BusyRegs[2], VT);
+    }
+
+    void addBusyReg(unsigned Reg) {
+      BusyRegs.push_back(convReg(Reg, MVT::i64));
+    }
+
+    void addBusyRegs(const X86Operand &Op) {
+      addBusyReg(Op.getMemBaseReg());
+      addBusyReg(Op.getMemIndexReg());
+    }
+
+    unsigned chooseFrameReg(MVT::SimpleValueType VT) const {
+      static const unsigned Candidates[] = { X86::RBP, X86::RAX, X86::RBX,
+                                             X86::RCX, X86::RDX, X86::RDI,
+                                             X86::RSI };
+      for (unsigned Reg : Candidates) {
+        if (!std::count(BusyRegs.begin(), BusyRegs.end(), Reg))
+          return convReg(Reg, VT);
+      }
+      return X86::NoRegister;
+    }
+
+  private:
+    unsigned convReg(unsigned Reg, MVT::SimpleValueType VT) const {
+      return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT);
     }
 
-    const unsigned AddressReg;
-    const unsigned ShadowReg;
-    const unsigned ScratchReg;
+    std::vector<unsigned> BusyRegs;
   };
 
   X86AddressSanitizer(const MCSubtargetInfo &STI)
       : X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
 
   virtual ~X86AddressSanitizer() {}
 
   // X86AsmInstrumentation implementation:
virtual void InstrumentAndEmitInstruction(const MCInst &Inst,
     InstrumentMOV(Inst, Operands, Ctx, MII, Out);
 
     RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
     if (!RepPrefix)
       EmitInstruction(Out, Inst);
   }
 
   // Adjusts up stack and saves all registers used in instrumentation.
   virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
                                             MCContext &Ctx,
                                             MCStreamer &Out) = 0;
 
   // Restores all registers used in instrumentation and adjusts stack.
   virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
                                             MCContext &Ctx,
                                             MCStreamer &Out) = 0;
 
void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
                                              unsigned AccessSize,
                                              MCContext &Ctx, MCStreamer &Out) {
   // FIXME: check whole ranges [DstReg .. DstReg + AccessSize * (CntReg - 1)]
   // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
   RegisterContext RegCtx(X86::RDX /* AddressReg */, X86::RAX /* ShadowReg */,
                          IsSmallMemAccess(AccessSize)
                              ? X86::RBX
                              : X86::NoRegister /* ScratchReg */);
+  RegCtx.addBusyReg(DstReg);
+  RegCtx.addBusyReg(SrcReg);
+  RegCtx.addBusyReg(CntReg);
 
   InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
 
   // Test (%SrcReg)
   {
     const MCExpr *Disp = MCConstantExpr::Create(0, Ctx);
     std::unique_ptr<X86Operand> Op(X86Operand::CreateMem(
         0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
   case X86::MOVAPSrm:
     AccessSize = 16;
     break;
   default:
     return;
   }
 
   const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
-  RegisterContext RegCtx(X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
-                         IsSmallMemAccess(AccessSize)
-                             ? X86::RCX
-                             : X86::NoRegister /* ScratchReg */);
 
   for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
     assert(Operands[Ix]);
     MCParsedAsmOperand &Op = *Operands[Ix];
     if (Op.isMem()) {
       X86Operand &MemOp = static_cast<X86Operand &>(Op);
+      RegisterContext RegCtx(
+          X86::RDI /* AddressReg */, X86::RAX /* ShadowReg */,
+          IsSmallMemAccess(AccessSize) ? X86::RCX
+                                       : X86::NoRegister /* ScratchReg */);
+      RegCtx.addBusyRegs(MemOp);
       InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
       InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out);
       InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
     }
   }
 }
 
 void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
                                                    MVT::SimpleValueType VT,
                                                    unsigned Reg, MCContext &Ctx,
                                                    MCStreamer &Out) {
public:
   void RestoreFlags(MCStreamer &Out) {
     EmitInstruction(Out, MCInstBuilder(X86::POPF32));
     OrigSPOffset += 4;
   }
 
   virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
                                             MCContext &Ctx,
                                             MCStreamer &Out) override {
+    unsigned LocalFrameReg = RegCtx.chooseFrameReg(MVT::i32);
+    assert(LocalFrameReg != X86::NoRegister);
+
     const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
     unsigned FrameReg = GetFrameReg(Ctx, Out);
     if (MRI && FrameReg != X86::NoRegister) {
-      SpillReg(Out, X86::EBP);
+      SpillReg(Out, LocalFrameReg);
       if (FrameReg == X86::ESP) {
-        Out.EmitCFIAdjustCfaOffset(4 /* byte size of the FrameReg */);
-        Out.EmitCFIRelOffset(MRI->getDwarfRegNum(X86::EBP, true /* IsEH */), 0);
+        Out.EmitCFIAdjustCfaOffset(4 /* byte size of the LocalFrameReg */);
+        Out.EmitCFIRelOffset(
+            MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
       }
       EmitInstruction(
-          Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EBP).addReg(FrameReg));
+          Out,
+          MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg));
       Out.EmitCFIRememberState();
-      Out.EmitCFIDefCfaRegister(MRI->getDwarfRegNum(X86::EBP, true /* IsEH */));
+      Out.EmitCFIDefCfaRegister(
+          MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
     }
 
     SpillReg(Out, RegCtx.addressReg(MVT::i32));
     SpillReg(Out, RegCtx.shadowReg(MVT::i32));
-    if (RegCtx.ScratchReg != X86::NoRegister)
+    if (RegCtx.scratchReg(MVT::i32) != X86::NoRegister)
       SpillReg(Out, RegCtx.scratchReg(MVT::i32));
     StoreFlags(Out);
   }
 
   virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
                                             MCContext &Ctx,
                                             MCStreamer &Out) override {
+    unsigned LocalFrameReg = RegCtx.chooseFrameReg(MVT::i32);
+    assert(LocalFrameReg != X86::NoRegister);
+
     RestoreFlags(Out);
-    if (RegCtx.ScratchReg != X86::NoRegister)
+    if (RegCtx.scratchReg(MVT::i32) != X86::NoRegister)
       RestoreReg(Out, RegCtx.scratchReg(MVT::i32));
     RestoreReg(Out, RegCtx.shadowReg(MVT::i32));
     RestoreReg(Out, RegCtx.addressReg(MVT::i32));
 
     unsigned FrameReg = GetFrameReg(Ctx, Out);
     if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
-      RestoreReg(Out, X86::EBP);
+      RestoreReg(Out, LocalFrameReg);
       Out.EmitCFIRestoreState();
       if (FrameReg == X86::ESP)
-        Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the FrameReg */);
+        Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the LocalFrameReg */);
     }
   }
 
   virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
                                          bool IsWrite,
                                          const RegisterContext &RegCtx,
                                          MCContext &Ctx,
                                          MCStreamer &Out) override;

 
 void X86AddressSanitizer32::InstrumentMemOperandSmall(
     X86Operand &Op, unsigned AccessSize, bool IsWrite,
     const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
   unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
   unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
   unsigned ShadowRegI8 = RegCtx.shadowReg(MVT::i8);
 
-  assert(RegCtx.ScratchReg != X86::NoRegister);
+  assert(RegCtx.scratchReg(MVT::i32) != X86::NoRegister);
   unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
 
   ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
 
   EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
                            AddressRegI32));
   EmitInstruction(Out, MCInstBuilder(X86::SHR32ri)
                            .addReg(ShadowRegI32)
public:
   void RestoreFlags(MCStreamer &Out) {
     EmitInstruction(Out, MCInstBuilder(X86::POPF64));
     OrigSPOffset += 8;
   }
 
   virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
                                             MCContext &Ctx,
                                             MCStreamer &Out) override {
+    unsigned LocalFrameReg = RegCtx.chooseFrameReg(MVT::i64);
+    assert(LocalFrameReg != X86::NoRegister);
+
     const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
     unsigned FrameReg = GetFrameReg(Ctx, Out);
     if (MRI && FrameReg != X86::NoRegister) {
       SpillReg(Out, X86::RBP);
       if (FrameReg == X86::RSP) {
-        Out.EmitCFIAdjustCfaOffset(8 /* byte size of the FrameReg */);
-        Out.EmitCFIRelOffset(MRI->getDwarfRegNum(X86::RBP, true /* IsEH */), 0);
+        Out.EmitCFIAdjustCfaOffset(8 /* byte size of the LocalFrameReg */);
+        Out.EmitCFIRelOffset(
+            MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0);
       }
       EmitInstruction(
-          Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RBP).addReg(FrameReg));
+          Out,
+          MCInstBuilder(X86::MOV64rr).addReg(LocalFrameReg).addReg(FrameReg));
       Out.EmitCFIRememberState();
-      Out.EmitCFIDefCfaRegister(MRI->getDwarfRegNum(X86::RBP, true /* IsEH */));
+      Out.EmitCFIDefCfaRegister(
+          MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */));
     }
 
     EmitAdjustRSP(Ctx, Out, -128);
     SpillReg(Out, RegCtx.shadowReg(MVT::i64));
     SpillReg(Out, RegCtx.addressReg(MVT::i64));
-    if (RegCtx.ScratchReg != X86::NoRegister)
+    if (RegCtx.scratchReg(MVT::i64) != X86::NoRegister)
       SpillReg(Out, RegCtx.scratchReg(MVT::i64));
     StoreFlags(Out);
   }
 
   virtual void InstrumentMemOperandEpilogue(const RegisterContext &RegCtx,
                                             MCContext &Ctx,
                                             MCStreamer &Out) override {
+    unsigned LocalFrameReg = RegCtx.chooseFrameReg(MVT::i64);
+    assert(LocalFrameReg != X86::NoRegister);
+
     RestoreFlags(Out);
-    if (RegCtx.ScratchReg != X86::NoRegister)
+    if (RegCtx.scratchReg(MVT::i64) != X86::NoRegister)
       RestoreReg(Out, RegCtx.scratchReg(MVT::i64));
     RestoreReg(Out, RegCtx.addressReg(MVT::i64));
     RestoreReg(Out, RegCtx.shadowReg(MVT::i64));
     EmitAdjustRSP(Ctx, Out, 128);
 
     unsigned FrameReg = GetFrameReg(Ctx, Out);
     if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
-      RestoreReg(Out, X86::RBP);
+      RestoreReg(Out, LocalFrameReg);
       Out.EmitCFIRestoreState();
       if (FrameReg == X86::RSP)
-        Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the FrameReg */);
+        Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the LocalFrameReg */);
     }
   }
 
   virtual void InstrumentMemOperandSmall(X86Operand &Op, unsigned AccessSize,
                                          bool IsWrite,
                                          const RegisterContext &RegCtx,
                                          MCContext &Ctx,
                                          MCStreamer &Out) override;
void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
     EmitInstruction(Out, MCInstBuilder(X86::CLD));
     EmitInstruction(Out, MCInstBuilder(X86::MMX_EMMS));
 
     EmitInstruction(Out, MCInstBuilder(X86::AND64ri8)
                              .addReg(X86::RSP)
                              .addReg(X86::RSP)
                              .addImm(-16));
 
-    if (RegCtx.AddressReg != X86::RDI) {
+    if (RegCtx.addressReg(MVT::i64) != X86::RDI) {
       EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RDI).addReg(
                                RegCtx.addressReg(MVT::i64)));
     }
     const std::string &Fn = FuncName(AccessSize, IsWrite);
     MCSymbol *FnSym = Ctx.GetOrCreateSymbol(StringRef(Fn));
     const MCSymbolRefExpr *FnExpr =
         MCSymbolRefExpr::Create(FnSym, MCSymbolRefExpr::VK_PLT, Ctx);
     EmitInstruction(Out, MCInstBuilder(X86::CALL64pcrel32).addExpr(FnExpr));
   }
 };
 
 void X86AddressSanitizer64::InstrumentMemOperandSmall(
     X86Operand &Op, unsigned AccessSize, bool IsWrite,
     const RegisterContext &RegCtx, MCContext &Ctx, MCStreamer &Out) {
   unsigned AddressRegI64 = RegCtx.addressReg(MVT::i64);
   unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
   unsigned ShadowRegI64 = RegCtx.shadowReg(MVT::i64);
   unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
   unsigned ShadowRegI8 = RegCtx.shadowReg(MVT::i8);
 
-  assert(RegCtx.ScratchReg != X86::NoRegister);
+  assert(RegCtx.scratchReg(MVT::i32) != X86::NoRegister);
   unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
 
   ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
 
   EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
                            AddressRegI64));
   EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
                            .addReg(ShadowRegI64)

test/Instrumentation/AddressSanitizer/X86/asm_cfi.s

 # The test verifies that correct DWARF directives are emitted when
 # assembly files are instrumented.
 
 # RUN: llvm-mc %s -triple=i386-unknown-linux-gnu -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
 
-# CHECK-LABEL: swap_cfa_rbp
-# CHECK: pushl %ebp
+# CHECK-LABEL: load4b_cfa_rbp
+# CHECK: pushl %ebx
 # CHECK-NOT: .cfi_adjust_cfa_offset 8
-# CHECK: movl %ebp, %ebp
+# CHECK: movl %ebp, %ebx
 # CHECK: .cfi_remember_state
-# CHECK: .cfi_def_cfa_register %ebp
-# CHECK: popl %ebp
+# CHECK: .cfi_def_cfa_register %ebx
+# CHECK: popl %ebx
 # CHECK: .cfi_restore_state
 # CHECK-NOT: .cfi_adjust_cfa_offset -8
 # CHECK: retl
 
   .text
-  .globl  swap_cfa_rbp
-  .type swap_cfa_rbp,@function
+  .globl  load4b_cfa_rbp
+  .type load4b_cfa_rbp,@function
 swap_cfa_rbp:                                   # @swap_cfa_rbp
   .cfi_startproc
   pushl %ebp
   .cfi_def_cfa_offset 8
   .cfi_offset %ebp, -8
   movl  %esp, %ebp
   .cfi_def_cfa_register %ebp
   movl  8(%ebp), %eax
-  movl  12(%ebp), %ecx
-  movl  (%ecx), %ecx
-  movl  %ecx, (%eax)
   popl  %ebp
   retl
   .cfi_endproc
 
-# CHECK-LABEL: swap_cfa_rsp
-# CHECK: pushl %ebp
+# CHECK-LABEL: load4b_cfa_rsp
+# CHECK: pushl %ebx
 # CHECK: .cfi_adjust_cfa_offset 4
-# CHECK: movl %esp, %ebp
+# CHECK: movl %esp, %ebx
 # CHECK: .cfi_remember_state
-# CHECK: .cfi_def_cfa_register %ebp
-# CHECK: popl %ebp
+# CHECK: .cfi_def_cfa_register %ebx
+# CHECK: popl %ebx
 # CHECK: .cfi_restore_state
 # CHECK: retl
 
-  .globl  swap_cfa_rsp
-  .type swap_cfa_rsp,@function
+  .globl  load4b_cfa_rsp
+  .type load4b_cfa_rsp,@function
 swap_cfa_rsp:                                   # @swap_cfa_rsp
   .cfi_startproc
   pushl %ebp
   .cfi_offset %ebp, 0
   movl  %esp, %ebp
   movl  8(%ebp), %eax
-  movl  12(%ebp), %ecx
-  movl  (%ecx), %ecx
-  movl  %ecx, (%eax)
   popl  %ebp
   retl
   .cfi_endproc