LLVM codegen test cases updated to check instructions generated when VSX is activated on Power

[seurer]

Summary

These test cases generate slightly different code sequences when VSX is activated and thus fail. The update turns off VSX explicitly for the existing checks and then adds a second set of checks for most of them that test the VSX instruction output.

[wschmidt]

This patch LGTM. Eric, any further concerns?

[wschmidt]

The patch itself is ok, but when I apply it to current trunk it exposes a crash in the VSX FMA mutation pass. If you can reproduce, please open a bug at llvm.org/bugs (against libraries/Backend:PowerPC). Crash follows:

/home/wschmidt/llvm/build/llvm-test/Release+Asserts/bin/llc < /home/wschmidt/ll\
vm/llvm-test/test/CodeGen/PowerPC/recipest.ll -mtriple=powerpc64-unknown-linux-\
gnu -mcpu=pwr7 -mattr=+vsx | /home/wschmidt/llvm/build/llvm-test/Release+Assert\
s/bin/FileCheck -check-prefix=CHECK-SAFE-VSX /home/wschmidt/llvm/llvm-test/test\

/CodeGen/PowerPC/recipest.ll

Exit Code: 2

Command Output (stderr):

llc: /home/wschmidt/llvm/llvm-test/lib/CodeGen/LiveInterval.cpp:299: llvm::Live\
Range::Segment* llvm::LiveRange::addSegmentFrom(llvm::LiveRange::Segment, llvm:\
:LiveRange::iterator): Assertion `B->end <= Start && "Cannot overlap two segmen\
ts with differing ValID's" " (did you def the same reg twice in a MachineInstr?\
)"' failed.
#0 0x1135fbac llvm::sys::PrintStackTrace(_IO_FILE*) (/home/wschmidt/llvm/build/\
llvm-test/Release+Asserts/bin/llc+0x1135fbac)
#1 0x1135fe44 PrintStackTraceSignalHandler(void*) (/home/wschmidt/llvm/build/ll\
vm-test/Release+Asserts/bin/llc+0x1135fe44)
#2 0x1135d754 SignalHandler(int) (/home/wschmidt/llvm/build/llvm-test/Release+A\
sserts/bin/llc+0x1135d754)
0 llc 0x000000001135fbac llvm::sys::PrintStackTrace(_IO_FILE*) + 92
1 llc 0x000000001135fe44
2 llc 0x000000001135d754
3 0x00003fff8fd00478 kernel_sigtramp_rt64 + 0
4 libc.so.6 0x00003fff8f820a88 gsignal + 72
5 libc.so.6 0x00003fff8f82693c abort + 620
6 libc.so.6 0x00003fff8f8165b4
7 libc.so.6 0x00003fff8f8166a4 assert_fail + 100
8 llc 0x0000000010c709f0 llvm::LiveRange::addSegmentFrom(llvm::LiveRange\
::Segment, llvm::LiveRange::Segment*) + 912
9 llc 0x0000000010845f34
10 llc 0x0000000010cdd178 llvm::MachineFunctionPass::runOnFunction(llvm::\
Function&) + 280
11 llc 0x00000000112cd880 llvm::FPPassManager::runOnFunction(llvm::Functi\
on&) + 640
12 llc 0x00000000112cdeec llvm::FPPassManager::runOnModule(llvm::Module&)\
+ 76
13 llc 0x00000000112ce308 llvm::legacy::PassManagerImpl::run(llvm::Module\
&) + 968
14 llc 0x00000000112ce5bc llvm::legacy::PassManager::run(llvm::Module&) +\
28
15 llc 0x0000000010243408
16 llc 0x000000001021bb10 main + 528
17 libc.so.6 0x00003fff8f804d00
18 libc.so.6 0x00003fff8f804ef8 __libc_start_main + 200
Stack dump:
0. Program arguments: /home/wschmidt/llvm/build/llvm-test/Release+Asserts/\
bin/llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math \
-mattr=+vsx

1. Running pass 'Function Pass Manager' on module '<stdin>'.
2. Running pass 'PowerPC VSX FMA Mutation' on function '@foo3'

FileCheck error: '-' is empty.

[wschmidt]

The crash was obtained with r219765 and your patch applied.

[wschmidt]

My recommendation would be to leave the recipest.ll test out of this patch for now, so the buildbots stay green. Instead, include the changes in the bugzilla so it can be added back when the bug is fixed.

[seurer]

Removed CodeGen/PowerPC/recipest.ll

[wschmidt]

This version LGTM and passes my testing. If no objections arise in the meantime, I'll commit this on seurer's behalf around 10 p.m. Central tonight.

[echristo]

I gather the reason for this patch is to increase the amount of testing that vsx gets while not just reusing the existing testcases and not writing new ones?

One small nit:

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vec_mul.ll

92

Newline.

[wschmidt]

The reason for the test is to correct the tests that generate different code when VSX is enabled (usually a vector-scalar version of the floating-point instruction, which has identical behavior but allows selection from 64 floating-point registers instead of 32). Hal already added quite a large number of VSX tests, and these complement those.

I should have commented on the newline -- I corrected that when I was testing his patch, so when i commit it that will be fixed.

[echristo]

OK, so the traditional way to do that would have been to just use a -mtriple on the command line to specify the exact machine you wanted to target rather than just using llc. If you want to test more code generation then this is fine, but if it's just random testing without purpose then I don't know if you want to keep it or not.

[wschmidt]

Except that currently there are no triples that generate VSX code because VSX code is disabled. The specific use of -mattr=+/-vsx allows us to get closer to enabling VSX, which is the end goal (moving target) of these patches. All of these incorrectly failing tests make it difficult to spot the actual problems. This seems the best way forward, and the extra VSX testing is a bonus.

[echristo]

The way to do that would, canonically, be -mtriple -mattr (similar to what you've been doing). It's just whether or not you want to add new tests for vsx specific things or not. I have no objections to this though.

[wschmidt]

Committed as r220019. This can be closed now.

[seurer]

Closing. Was committed as r220019.

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/2007-09-08-unaligned.ll

-; RUN: llc < %s | grep stfd | count 3
-; RUN: llc < %s | grep stfs | count 1
-; RUN: llc < %s | grep lfd | count 2
-; RUN: llc < %s | grep lfs | count 2
+; RUN: llc -mattr=-vsx < %s | grep stfd | count 3
+; RUN: llc -mattr=-vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=-vsx < %s | grep lfd | count 2
+; RUN: llc -mattr=-vsx < %s | grep lfs | count 2
+; RUN: llc -mattr=+vsx < %s | grep stxsdx | count 3
+; RUN: llc -mattr=+vsx < %s | grep stfs | count 1
+; RUN: llc -mattr=+vsx < %s | grep lxsdx | count 2
+; RUN: llc -mattr=+vsx < %s | grep lfs | count 2
 ; ModuleID = 'foo.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
 target triple = "powerpc-apple-darwin8"
   %struct.anon = type <{ i8, float }>
 @s = global %struct.anon <{ i8 3, float 0x4014666660000000 }>    ; <%struct.anon*> [#uses=1]
 @u = global <{ i8, double }> <{ i8 3, double 5.100000e+00 }>    ; <<{ i8, double }>*> [#uses=1]
 @t = weak global %struct.anon zeroinitializer   ; <%struct.anon*> [#uses=2]
 @v = weak global <{ i8, double }> zeroinitializer    ; <<{ i8, double }>*> [#uses=2]

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/2012-10-12-bitcast.ll

-; RUN: llc -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=-vsx -mattr=+altivec < %s | FileCheck %s
+; RUN: llc -mattr=+vsx -mattr=+altivec < %s | FileCheck -check-prefix=CHECK-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @test(<16 x i8> %v) nounwind {
 entry:
   %0 = bitcast <16 x i8> %v to i128
   %1 = lshr i128 %0, 96
   %2 = trunc i128 %1 to i32
   ret i32 %2
 }
 
 ; Verify that bitcast handles big-endian platforms correctly
 ; by checking we load the result from the correct offset
 
 ; CHECK: addi [[REGISTER:[0-9]+]], 1, -16
 ; CHECK: stvx 2, 0, [[REGISTER]]
 ; CHECK: lwz 3, -16(1)
 ; CHECK: blr
 
+; CHECK-VSX: addi [[REGISTER:[0-9]+]], 1, -16
+; CHECK-VSX: stxvd2x 34, 0, [[REGISTER]]
+; CHECK-VSX: lwz 3, -16(1)
+; CHECK-VSX: blr

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/buildvec_canonicalize.ll

-; RUN: llc < %s -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck %s
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+altivec --enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-VSX %s
 
 define void @VXOR(<4 x float>* %P1, <4 x i32>* %P2, <4 x float>* %P3) {
         %tmp = load <4 x float>* %P3            ; <<4 x float>> [#uses=1]
         %tmp3 = load <4 x float>* %P1           ; <<4 x float>> [#uses=1]
         %tmp4 = fmul <4 x float> %tmp, %tmp3             ; <<4 x float>> [#uses=1]
         store <4 x float> %tmp4, <4 x float>* %P3
         store <4 x float> zeroinitializer, <4 x float>* %P1
         store <4 x i32> zeroinitializer, <4 x i32>* %P2
         ret void
 }
 ; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
 ; to vmaddfp (so it would IEEE compliant with zero sign propagation).
 ; CHECK: @VXOR
 ; CHECK: vsplti
 ; CHECK: vxor
+; CHECK-VSX: @VXOR
+; CHECK-VSX: vxor
+; CHECK-VSX: xvmulsp
 
 define void @VSPLTI(<4 x i32>* %P2, <8 x i16>* %P3) {
         store <4 x i32> bitcast (<16 x i8> < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > to <4 x i32>), <4 x i32>* %P2
         store <8 x i16> < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >, <8 x i16>* %P3
         ret void
 }
 ; CHECK: @VSPLTI
 ; CHECK: vsplti
+; CHECK-VSX: @VSPLTI
+; CHECK-VSX: vsplti

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/copysignl.ll

-; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s -check-prefix=CHECK-VSX
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @foo_d_ll(ppc_fp128 %a, ppc_fp128 %b) #0 {
 entry:
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %a, ppc_fp128 %b) #0
   %conv = fptrunc ppc_fp128 %call to double
   ret double %conv
 
 ; CHECK-LABEL: @foo_d_ll
 ; CHECK: fcpsgn 1, 3, 1
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_d_ll
+; CHECK-VSX: xscpsgndp 1, 3, 1
+; CHECK-VSX: blr
 }
 
 declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) #0
 
 define double @foo_dl(double %a, ppc_fp128 %b) #0 {
 entry:
   %conv = fptrunc ppc_fp128 %b to double
   %call = tail call double @copysign(double %a, double %conv) #0
   ret double %call
 
 ; CHECK-LABEL: @foo_dl
 ; CHECK: fcpsgn 1, 2, 1
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_dl
+; CHECK-VSX: xscpsgndp 1, 2, 1
+; CHECK-VSX: blr
 }
 
 declare double @copysign(double, double) #0
 
 define ppc_fp128 @foo_ll(double %a, ppc_fp128 %b) #0 {
 entry:
   %conv = fpext double %a to ppc_fp128
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %b) #0
   ret ppc_fp128 %call
 
 ; CHECK-LABEL: @foo_ll
 ; CHECK: bl copysignl
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_ll
+; CHECK-VSX: bl copysignl
+; CHECK-VSX: blr
 }
 
 define ppc_fp128 @foo_ld(double %a, double %b) #0 {
 entry:
   %conv = fpext double %a to ppc_fp128
   %conv1 = fpext double %b to ppc_fp128
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0
   ret ppc_fp128 %call
 
 ; CHECK-LABEL: @foo_ld
 ; CHECK: bl copysignl
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_ld
+; CHECK-VSX: bl copysignl
+; CHECK-VSX: blr
 }
 
 define ppc_fp128 @foo_lf(double %a, float %b) #0 {
 entry:
   %conv = fpext double %a to ppc_fp128
   %conv1 = fpext float %b to ppc_fp128
   %call = tail call ppc_fp128 @copysignl(ppc_fp128 %conv, ppc_fp128 %conv1) #0
   ret ppc_fp128 %call
 
 ; CHECK-LABEL: @foo_lf
 ; CHECK: bl copysignl
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_lf
+; CHECK-VSX: bl copysignl
+; CHECK-VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/fabs.ll

-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "xsabsdp f1, f1"
 
 define double @fabs(double %f) {
 entry:
   %tmp2 = tail call double @fabs( double %f ) readnone  ; <double> [#uses=1]
   ret double %tmp2
 }

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/fcpsgn.ll

-; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @foo_dd(double %a, double %b) #0 {
 entry:
   %call = tail call double @copysign(double %a, double %b) #0
   ret double %call
 
 ; CHECK-LABEL: @foo_dd
 ; CHECK: fcpsgn 1, 2, 1
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_dd
+; CHECK-VSX: xscpsgndp 1, 2, 1
+; CHECK-VSX: blr
 }
 
 declare double @copysign(double, double) #0
 
 define float @foo_ss(float %a, float %b) #0 {
 entry:
   %call = tail call float @copysignf(float %a, float %b) #0
   ret float %call
 
 ; CHECK-LABEL: @foo_ss
 ; CHECK: fcpsgn 1, 2, 1
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_ss
+; CHECK-VSX: fcpsgn 1, 2, 1
+; CHECK-VSX: blr
 }
 
 declare float @copysignf(float, float) #0
 
 define float @foo_sd(float %a, double %b) #0 {
 entry:
   %conv = fptrunc double %b to float
   %call = tail call float @copysignf(float %a, float %conv) #0
   ret float %call
 
 ; CHECK-LABEL: @foo_sd
 ; CHECK: fcpsgn 1, 2, 1
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_sd
+; CHECK-VSX: fcpsgn 1, 2, 1
+; CHECK-VSX: blr
 }
 
 define double @foo_ds(double %a, float %b) #0 {
 entry:
   %conv = fpext float %b to double
   %call = tail call double @copysign(double %a, double %conv) #0
   ret double %call
 
 ; CHECK-LABEL: @foo_ds
 ; CHECK: fcpsgn 1, 2, 1
 ; CHECK: blr
+; CHECK-VSX-LABEL: @foo_ds
+; CHECK-VSX: fcpsgn 1, 2, 1
+; CHECK-VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/fnabs.ll

-; RUN: llc < %s -march=ppc32 | grep fnabs
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fnabs
+; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xsnabsdp
 
 declare double @fabs(double)
 
 define double @test(double %X) {
         %Y = call double @fabs( double %X ) readnone     ; <double> [#uses=1]
         %Z = fsub double -0.000000e+00, %Y               ; <double> [#uses=1]
         ret double %Z
 }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/fp-branch.ll

-; RUN: llc < %s -march=ppc32 | grep fcmp | count 1
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fcmp | count 1
+; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xscmpudp | count 1
 
 declare i1 @llvm.isunordered.f64(double, double)
 
 define i1 @intcoord_cond_next55(double %tmp48.reload) {
 newFuncRoot:
         br label %cond_next55
 
 bb72.exitStub:          ; preds = %cond_next55

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/fp_to_uint.ll

-; RUN: llc < %s -march=ppc32 | grep fctiwz | count 1
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fctiwz | count 1
+; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xscvdpsxws | count 1
+
 
 define i16 @foo(float %a) {
 entry:
         %tmp.1 = fptoui float %a to i16         ; <i16> [#uses=1]
         ret i16 %tmp.1
 }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/fsel.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @zerocmp1(double %a, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ult double %a, 0.000000e+00
   %z.y = select i1 %cmp, double %z, double %y
   ret double %z.y
 
 ; CHECK: @zerocmp1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @zerocmp1
 ; CHECK-FM: fsel 1, 1, 2, 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp1
+; CHECK-FM-VSX: fsel 1, 1, 2, 3
+; CHECK-FM-VSX: blr
 }
 
 define double @zerocmp2(double %a, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ogt double %a, 0.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @zerocmp2
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @zerocmp2
 ; CHECK-FM: fneg [[REG:[0-9]+]], 1
 ; CHECK-FM: fsel 1, [[REG]], 3, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp2
+; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @zerocmp3(double %a, double %y, double %z) #0 {
 entry:
   %cmp = fcmp oeq double %a, 0.000000e+00
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @zerocmp3
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @zerocmp3
 ; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3
 ; CHECK-FM: fneg [[REG2:[0-9]+]], 1
 ; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @zerocmp3
+; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1
+; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
+; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
+; CHECK-FM-VSX: blr
 }
 
 define double @min1(double %a, double %b) #0 {
 entry:
   %cmp = fcmp ole double %a, %b
   %cond = select i1 %cmp, double %a, double %b
   ret double %cond
 
 ; CHECK: @min1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @min1
 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
 ; CHECK-FM: fsel 1, [[REG]], 1, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @min1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @max1(double %a, double %b) #0 {
 entry:
   %cmp = fcmp oge double %a, %b
   %cond = select i1 %cmp, double %a, double %b
   ret double %cond
 
 ; CHECK: @max1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @max1
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel 1, [[REG]], 1, 2
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @max1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp1(double %a, double %b, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ult double %a, %b
   %z.y = select i1 %cmp, double %z, double %y
   ret double %z.y
 
 ; CHECK: @cmp1
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @cmp1
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel 1, [[REG]], 3, 4
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp1
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp2(double %a, double %b, double %y, double %z) #0 {
 entry:
   %cmp = fcmp ogt double %a, %b
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @cmp2
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @cmp2
 ; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
 ; CHECK-FM: fsel 1, [[REG]], 4, 3
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp2
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3
+; CHECK-FM-VSX: blr
 }
 
 define double @cmp3(double %a, double %b, double %y, double %z) #0 {
 entry:
   %cmp = fcmp oeq double %a, %b
   %y.z = select i1 %cmp, double %y, double %z
   ret double %y.z
 
 ; CHECK: @cmp3
 ; CHECK-NOT: fsel
 ; CHECK: blr
 
 ; CHECK-FM: @cmp3
 ; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
 ; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
 ; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]
 ; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4
 ; CHECK-FM: blr
+
+; CHECK-FM-VSX: @cmp3
+; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
+; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
+; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4
+; CHECK-FM-VSX: blr
 }
 
 attributes #0 = { nounwind readnone }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/fsqrt.ll

 ; fsqrt should be generated when the fsqrt feature is enabled, but not 
 ; otherwise.
 
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=+fsqrt | \
 ; RUN:   grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g5 | \
 ; RUN:   grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mattr=-fsqrt | \
 ; RUN:   not grep "fsqrt f1, f1"
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin8 -mcpu=g4 | \
 ; RUN:   not grep "fsqrt f1, f1"
 
 declare double @llvm.sqrt.f64(double)
 
 define double @X(double %Y) {
         %Z = call double @llvm.sqrt.f64( double %Y )            ; <double> [#uses=1]
         ret double %Z
 }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/i64_fp.ll

 ; fcfid and fctid should be generated when the 64bit feature is enabled, but not
 ; otherwise.
 
-; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \
 ; RUN:   grep fcfid
-; RUN: llc < %s -march=ppc32 -mattr=+64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=+64bit | \
 ; RUN:   grep fctidz
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \
 ; RUN:   grep fcfid
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g5 | \
 ; RUN:   grep fctidz
-; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \
 ; RUN:   not grep fcfid
-; RUN: llc < %s -march=ppc32 -mattr=-64bit | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mattr=-64bit | \
 ; RUN:   not grep fctidz
-; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \
 ; RUN:   not grep fcfid
-; RUN: llc < %s -march=ppc32 -mcpu=g4 | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mcpu=g4 | \
 ; RUN:   not grep fctidz
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+64bit | \
+; RUN:   grep xscvdpsxds
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -mattr=+64bit | \
+; RUN:   grep xscvsxddp
 
 define double @X(double %Y) {
         %A = fptosi double %Y to i64            ; <i64> [#uses=1]
         %B = sitofp i64 %A to double            ; <double> [#uses=1]
         ret double %B
 }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/mcm-12.ll

-; RUN: llc -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O1 -code-model=medium -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O1 -code-model=medium -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
 
 ; Test peephole optimization for medium code model (32-bit TOC offsets)
 ; for loading a value from the constant pool (TOC-relative).
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
 ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
 ; CHECK: .quad 4562098671269285104
 ; CHECK-LABEL: test_double_const:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
+
+; CHECK-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; CHECK-VSX: .quad 4562098671269285104
+; CHECK-VSX-LABEL: test_double_const:
+; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; CHECK-VSX: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l
+; CHECK-VSX: lxsdx {{[0-9]+}}, 0, [[REG1]]

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/mcm-4.ll

-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false <%s | FileCheck -check-prefix=MEDIUM %s
-; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false <%s | FileCheck -check-prefix=LARGE %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=large -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s
 
 ; Test correct code generation for medium and large code model
 ; for loading a value from the constant pool (TOC-relative).
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define double @test_double_const() nounwind {
 entry:
   ret double 0x3F4FD4920B498CF0
 }
 
 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
 ; MEDIUM: .quad 4562098671269285104
 ; MEDIUM-LABEL: test_double_const:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
 
+; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; MEDIUM-VSX: .quad 4562098671269285104
+; MEDIUM-VSX-LABEL: test_double_const:
+; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
+; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
+; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
+
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 4562098671269285104
 ; LARGE-LABEL: test_double_const:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
+
+; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:
+; LARGE-VSX: .quad 4562098671269285104
+; LARGE-VSX-LABEL: test_double_const:
+; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
+; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
+; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/ppc64-align-long-double.ll

-; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -fast-isel=false -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
 
 ; Verify internal alignment of long double in a struct.  The double
 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
 ; the long double.  Check that these are stored to proper locations
 ; in the parameter save area and loaded from there for return in FPR1/2.
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"

 
 ; CHECK: std 6, 72(1)
 ; CHECK: std 5, 64(1)
 ; CHECK: std 4, 56(1)
 ; CHECK: std 3, 48(1)
 ; CHECK: lfd 1, 64(1)
 ; CHECK: lfd 2, 72(1)
 
+; CHECK-VSX: std 6, 72(1)
+; CHECK-VSX: std 5, 64(1)
+; CHECK-VSX: std 4, 56(1)
+; CHECK-VSX: std 3, 48(1)
+; CHECK-VSX: li 3, 16
+; CHECK-VSX: addi 4, 1, 48
+; CHECK-VSX: lxsdx 1, 4, 3
+; CHECK-VSX: li 3, 24
+; CHECK-VSX: lxsdx 2, 4, 3

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/rounding-ops.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
 ; CHECK-LABEL: test1:
 ; CHECK: frim 1, 1
+; CHECK-VSX-LABEL: test1:
+; CHECK-VSX: frim 1, 1
 }
 
 declare float @floorf(float) nounwind readnone
 
 define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
 ; CHECK-LABEL: test2:
 ; CHECK: frim 1, 1
+; CHECK-VSX-LABEL: test2:
+; CHECK-VSX: xsrdpim 1, 1
 }
 
 declare double @floor(double) nounwind readnone
 
 define float @test3(float %x) nounwind  {
   %call = tail call float @roundf(float %x) nounwind readnone
   ret float %call
 
 ; CHECK-LABEL: test3:
 ; CHECK: frin 1, 1
+; CHECK-VSX-LABEL: test3:
+; CHECK-VSX: frin 1, 1
 }
 
 declare float @roundf(float) nounwind readnone
 
 define double @test4(double %x) nounwind  {
   %call = tail call double @round(double %x) nounwind readnone
   ret double %call
 
 ; CHECK-LABEL: test4:
 ; CHECK: frin 1, 1
+; CHECK-VSX-LABEL: test4:
+; CHECK-VSX: xsrdpi 1, 1
 }
 
 declare double @round(double) nounwind readnone
 
 define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
 ; CHECK-LABEL: test5:
 ; CHECK: frip 1, 1
+; CHECK-VSX-LABEL: test5:
+; CHECK-VSX: frip 1, 1
 }
 
 declare float @ceilf(float) nounwind readnone
 
 define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
 ; CHECK-LABEL: test6:
 ; CHECK: frip 1, 1
+; CHECK-VSX-LABEL: test6:
+; CHECK-VSX: xsrdpip 1, 1
 }
 
 declare double @ceil(double) nounwind readnone
 
 define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
 ; CHECK-LABEL: test9:
 ; CHECK: friz 1, 1
+; CHECK-VSX-LABEL: test9:
+; CHECK-VSX: friz 1, 1
 }
 
 declare float @truncf(float) nounwind readnone
 
 define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
 ; CHECK-LABEL: test10:
 ; CHECK: friz 1, 1
+; CHECK-VSX-LABEL: test10:
+; CHECK-VSX: xsrdpiz 1, 1
 }
 
 declare double @trunc(double) nounwind readnone
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/unaligned.ll

-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 
 define void @foo1(i16* %p, i16* %r) nounwind {
 entry:
   %v = load i16* %p, align 1
   store i16 %v, i16* %r, align 1
   ret void
 
 ; CHECK: @foo1
 ; CHECK: lhz
 ; CHECK: sth
+
+; CHECK-VSX: @foo1
+; CHECK-VSX: lhz
+; CHECK-VSX: sth
 }
 
 define void @foo2(i32* %p, i32* %r) nounwind {
 entry:
   %v = load i32* %p, align 1
   store i32 %v, i32* %r, align 1
   ret void
 
 ; CHECK: @foo2
 ; CHECK: lwz
 ; CHECK: stw
+
+; CHECK-VSX: @foo2
+; CHECK-VSX: lwz
+; CHECK-VSX: stw
 }
 
 define void @foo3(i64* %p, i64* %r) nounwind {
 entry:
   %v = load i64* %p, align 1
   store i64 %v, i64* %r, align 1
   ret void
 
 ; CHECK: @foo3
 ; CHECK: ld
 ; CHECK: std
+
+; CHECK-VSX: @foo3
+; CHECK-VSX: ld
+; CHECK-VSX: std
 }
 
 define void @foo4(float* %p, float* %r) nounwind {
 entry:
   %v = load float* %p, align 1
   store float %v, float* %r, align 1
   ret void
 
 ; CHECK: @foo4
 ; CHECK: lfs
 ; CHECK: stfs
+
+; CHECK-VSX: @foo4
+; CHECK-VSX: lfs
+; CHECK-VSX: stfs
 }
 
 define void @foo5(double* %p, double* %r) nounwind {
 entry:
   %v = load double* %p, align 1
   store double %v, double* %r, align 1
   ret void
 
 ; CHECK: @foo5
 ; CHECK: lfd
 ; CHECK: stfd
+
+; CHECK-VSX: @foo5
+; CHECK-VSX: lxsdx
+; CHECK-VSX: stxsdx
 }
 
 define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {
 entry:
   %v = load <4 x float>* %p, align 1
   store <4 x float> %v, <4 x float>* %r, align 1
   ret void
 
 ; These loads and stores are legalized into aligned loads and stores
 ; using aligned stack slots.
 ; CHECK: @foo6
 ; CHECK-DAG: ld
 ; CHECK-DAG: ld
 ; CHECK-DAG: stdx
 ; CHECK: stdx
+
+; CHECK-VSX: @foo6
+; CHECK-VSX-DAG: ld
+; CHECK-VSX-DAG: ld
+; CHECK-VSX-DAG: stdx
+; CHECK-VSX: stdx
 }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/unsafe-math.ll

-; RUN: llc < %s -march=ppc32 | grep fmul | count 2
-; RUN: llc < %s -march=ppc32 -enable-unsafe-fp-math | \
+; RUN: llc < %s -mattr=-vsx -march=ppc32 | grep fmul | count 2
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -enable-unsafe-fp-math | \
 ; RUN:   grep fmul | count 1
+; RUN: llc < %s -mattr=+vsx -march=ppc32 | grep xsmuldp | count 2
+; RUN: llc < %s -mattr=+vsx -march=ppc32 -enable-unsafe-fp-math | \
+; RUN:   grep xsmuldp | count 1
 
 define double @foo(double %X) nounwind {
         %tmp1 = fmul double %X, 1.23
         %tmp2 = fmul double %tmp1, 4.124
         ret double %tmp2
 }
 

/home/seurer/llvm/llvm-oneoff/test/CodeGen/PowerPC/vec_mul.ll

-; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s -check-prefix=CHECK-LE
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-LE-VSX
 
 define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
   %tmp = load <4 x i32>* %X    ; <<4 x i32>> [#uses=1]
   %tmp2 = load <4 x i32>* %Y    ; <<4 x i32>> [#uses=1]
   %tmp3 = mul <4 x i32> %tmp, %tmp2    ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %tmp3
 }
 ; CHECK-LABEL: test_v4i32:
 ; CHECK: vmsumuhm
 ; CHECK-NOT: mullw
 ; CHECK-LE-LABEL: test_v4i32:
 ; CHECK-LE: vmsumuhm
 ; CHECK-LE-NOT: mullw
+; CHECK-VSX-LABEL: test_v4i32:
+; CHECK-VSX: vmsumuhm
+; CHECK-VSX-NOT: mullw
+; CHECK-LE-VSX-LABEL: test_v4i32:
+; CHECK-LE-VSX: vmsumuhm
+; CHECK-LE-VSX-NOT: mullw
 
 define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
   %tmp = load <8 x i16>* %X    ; <<8 x i16>> [#uses=1]
   %tmp2 = load <8 x i16>* %Y    ; <<8 x i16>> [#uses=1]
   %tmp3 = mul <8 x i16> %tmp, %tmp2    ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %tmp3
 }
 ; CHECK-LABEL: test_v8i16:
 ; CHECK: vmladduhm
 ; CHECK-NOT: mullw
 ; CHECK-LE-LABEL: test_v8i16:
 ; CHECK-LE: vmladduhm
 ; CHECK-LE-NOT: mullw
+; CHECK-VSX-LABEL: test_v8i16:
+; CHECK-VSX: vmladduhm
+; CHECK-VSX-NOT: mullw
+; CHECK-LE-VSX-LABEL: test_v8i16:
+; CHECK-LE-VSX: vmladduhm
+; CHECK-LE-VSX-NOT: mullw
 
 define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
   %tmp = load <16 x i8>* %X    ; <<16 x i8>> [#uses=1]
   %tmp2 = load <16 x i8>* %Y    ; <<16 x i8>> [#uses=1]
   %tmp3 = mul <16 x i8> %tmp, %tmp2    ; <<16 x i8>> [#uses=1]
   ret <16 x i8> %tmp3
 }
 ; CHECK-LABEL: test_v16i8:
 ; CHECK: vmuloub
 ; CHECK: vmuleub
 ; CHECK-NOT: mullw
 ; CHECK-LE-LABEL: test_v16i8:
 ; CHECK-LE: vmuloub [[REG1:[0-9]+]]
 ; CHECK-LE: vmuleub [[REG2:[0-9]+]]
 ; CHECK-LE: vperm {{[0-9]+}}, [[REG2]], [[REG1]]
 ; CHECK-LE-NOT: mullw
+; CHECK-VSX-LABEL: test_v16i8:
+; CHECK-VSX: vmuloub
+; CHECK-VSX: vmuleub
+; CHECK-VSX-NOT: mullw
+; CHECK-LE-VSX-LABEL: test_v16i8:
+; CHECK-LE-VSX: vmuloub [[REG1:[0-9]+]]
+; CHECK-LE-VSX: vmuleub [[REG2:[0-9]+]]
+; CHECK-LE-VSX: vperm {{[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK-LE-VSX-NOT: mullw
 
 define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
   %tmp = load <4 x float>* %X
   %tmp2 = load <4 x float>* %Y
   %tmp3 = fmul <4 x float> %tmp, %tmp2
   ret <4 x float> %tmp3
 }
 ; Check the creation of a negative zero float vector by creating a vector of
 ; all bits set and shifting it 31 bits to left, resulting a an vector of 
 ; 4 x 0x80000000 (-0.0 as float).
 ; CHECK-LABEL: test_float:
 ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
 ; CHECK: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
 ; CHECK: vmaddfp
 ; CHECK-LE-LABEL: test_float:
 ; CHECK-LE: vspltisw [[ZNEG:[0-9]+]], -1
 ; CHECK-LE: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
 ; CHECK-LE: vmaddfp
+; CHECK-VSX-LABEL: test_float:
+; CHECK-VSX: xvmulsp
+; CHECK-LE-VSX-LABEL: test_float:
+; CHECK-LE-VSX: xvmulsp
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