Add mips32 r1 to the list of supported targets for Mips fast-isel

[rkotler]

Summary

Expand list of supported targets for Mips to include mips32 r1.
Previously it only include r2. More patches are coming where there is
a difference but in the current patches as pushed upstream, r1 and r2
are equivalent.

[dsanders]

LGTM with the change to simplestore.ll made to the other existing fast isel tests as well.

[rkotler]

• fix test cases

[rkotler]

Not fully ready for checking. There is a difference regarding the floating point test that needs to be resolved.
simplestorefp1.ll

Why is this pattern restricted to mips32r2?

def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,

MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;

def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,

              MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> {
let DecoderNamespace = "Mips64";

}

I'm getting a difference when I do fast-isel on one test case, depending on mips32r1 and mips32r2

69c69

< mtc1 $25, $f1

mthc1    $25, $f0

Any special things that are done in isel lowering and dagtodag are not going to be available to fast-isel.

In fast-isel the MHTC1 is not emitted in function d1.

This happens if I apply my patch to tip of tree.

; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s

@f = common global float 0.000000e+00, align 4
@de = common global double 0.000000e+00, align 8

; Function Attrs: nounwind
define void @f1() #0 {
entry:

store float 0x3FFA76C8C0000000, float* @f, align 4
ret void

; CHECK: .ent f1
; CHECK: lui $[[REG1:[0-9]+]], 16339
; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 46662
; CHECK: mtc1 $[[REG2]], $f[[REG3:[0-9]+]]
; CHECK: lw $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
; CHECK: swc1 $f[[REG3]], 0($[[REG4]])
; CHECK: .end f1

}

; Function Attrs: nounwind
define void @d1() #0 {
entry:

store double 1.234567e+00, double* @de, align 8

; CHECK: .ent d1
; CHECK: lui $[[REG1a:[0-9]+]], 16371
; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
; CHECK: lui $[[REG1b:[0-9]+]], 21403
; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
; CHECK: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
; CHECK: mthc1 $[[REG2a]], $f[[REG3]]
; CHECK: sdc1 $f[[REG3]], 0(${{[0-9]+}})
; CHECK: .end d1

ret void

}

[dsanders]

mthc1 was added in mips32r2 as part of the support for 64-bit fpu's on a 32-bit cpu. One other thing to mention is that -mfpxx prohibits the use of mtc1 on an odd-numbered FPU register in order to make the generated code mode-agnostic. Since mthc1 isn't available on mips32 and earlier, you have to spill/reload using sdc1/ldc1 instead.

I don't mind if you temporarily XFAIL the test and fix it in a follow-up.

[rkotler]

So then this code for mips32r1 looks okay? foo1.s is r1, foo2.s is r2

~/llvm-push/build/Debug+Asserts/bin/llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 simplestorefp1.ll -o foo2.s

rkotler@ubuntu-rkotler:~/testmips/calling$ diff foo1.s foo2.s -c4

• foo1.s 2014-09-14 18:15:27.987385000 -0700
• foo2.s 2014-09-14 18:16:41.876205000 -0700 ***
• 65,73 **** ori $25, $25, 49353 lui $1, 21403 ori $1, $1, 34951 mtc1 $1, $f0

! mtc1 $25, $f1

	lw	$1, %got(de)($2)
	sdc1	$f0, 0($1)
	move	 $sp, $fp
	lw	$fp, 4($sp)             # 4-byte Folded Reload

• 65,73 ---- ori $25, $25, 49353 lui $1, 21403 ori $1, $1, 34951 mtc1 $1, $f0

! mthc1 $25, $f0

	lw	$1, %got(de)($2)
	sdc1	$f0, 0($1)
	move	 $sp, $fp
	lw	$fp, 4($sp)             # 4-byte Folded Reload

[rkotler]

• fix test case

[rkotler]

Rather than XFAIL the test case I fixed the test case for mips32r1 and verified that on actual hardware that this sequence works on that rev.

[dsanders]

Yes, that MIPS32r1 code is correct when -mfpxx is not in effect. When -mfpxx is in effect, it should be using a spill and reload using 'sd' and 'ldc1' instead.

In D5306#14, @rkotler wrote:

Rather than XFAIL the test case I fixed the test case for mips32r1 and verified that on actual hardware that this sequence works on that rev.

That's great. Thanks

lib/Target/Mips/MipsFastISel.cpp

explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
         M(const_cast<Module &>(*funcInfo.Fn->getParent())),
         TM(funcInfo.MF->getTarget()),
         TII(*TM.getSubtargetImpl()->getInstrInfo()),
         TLI(*TM.getSubtargetImpl()->getTargetLowering()),
         Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
     MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
     Context = &funcInfo.Fn->getContext();
     TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
-                       (Subtarget->hasMips32r2() && (Subtarget->isABI_O32())));
+                       ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
+                        (Subtarget->isABI_O32())));
   }
 
   bool fastSelectInstruction(const Instruction *I) override;
   unsigned fastMaterializeConstant(const Constant *C) override;
 
   bool ComputeAddress(const Value *Obj, Address &Addr);
 
 private:

test/CodeGen/Mips/Fast-ISel/loadstore2.ll

 ; ModuleID = 'loadstore2.c'
 target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
 target triple = "mips--linux-gnu"
 
 @c2 = common global i8 0, align 1
 @c1 = common global i8 0, align 1
 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
 
 @s2 = common global i16 0, align 2
 @s1 = common global i16 0, align 2
 @i2 = common global i32 0, align 4
 @i1 = common global i32 0, align 4
 @f2 = common global float 0.000000e+00, align 4
 @f1 = common global float 0.000000e+00, align 4
 @d2 = common global double 0.000000e+00, align 8

test/CodeGen/Mips/Fast-ISel/loadstrconst.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
 
 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
 @s = common global i8* null, align 4
 
 ; Function Attrs: nounwind
 define void @foo() #0 {
 entry:
   store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** @s, align 4

test/CodeGen/Mips/Fast-ISel/nullvoid.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
 
 ; Function Attrs: nounwind
 define void @foo() {
 entry:
   ret void
 ; CHECK: jr $ra
 }

test/CodeGen/Mips/Fast-ISel/simplestore.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
 
 @abcd = external global i32
 
 ; Function Attrs: nounwind
 define void @foo()  {
 entry:
   store i32 12345, i32* @abcd, align 4
 ; CHECK:  addiu $[[REG1:[0-9]+]], $zero, 12345
 ; CHECK:  lw  $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
 ; CHECK:  sw  $[[REG1]], 0($[[REG2]])
   ret void
 }
 

test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
-; RUN:     < %s | FileCheck %s
+; RUN:     < %s | FileCheck %s 
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN:     < %s | FileCheck %s -check-prefix=mips32r2 
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s -check-prefix=mips32
 
 @f = common global float 0.000000e+00, align 4
 @de = common global double 0.000000e+00, align 8
 
 ; Function Attrs: nounwind
 define void @f1() #0 {
 entry:
   store float 0x3FFA76C8C0000000, float* @f, align 4
   ret void
 ; CHECK:  .ent  f1
 ; CHECK:  lui  $[[REG1:[0-9]+]], 16339
 ; CHECK:  ori  $[[REG2:[0-9]+]], $[[REG1]], 46662
 ; CHECK:  mtc1  $[[REG2]], $f[[REG3:[0-9]+]]
 ; CHECK:  lw  $[[REG4:[0-9]+]], %got(f)(${{[0-9]+}})
 ; CHECK:  swc1  $f[[REG3]], 0($[[REG4]])
 ; CHECK:   .end  f1
 
 }
 
 ; Function Attrs: nounwind
 define void @d1() #0 {
 entry:
   store double 1.234567e+00, double* @de, align 8
-; CHECK:  .ent  d1
-; CHECK:  lui  $[[REG1a:[0-9]+]], 16371
-; CHECK:  ori  $[[REG2a:[0-9]+]], $[[REG1a]], 49353
-; CHECK:  lui  $[[REG1b:[0-9]+]], 21403
-; CHECK:  ori  $[[REG2b:[0-9]+]], $[[REG1b]], 34951
-; CHECK:  mtc1  $[[REG2b]], $f[[REG3:[0-9]+]]
-; CHECK:  mthc1  $[[REG2a]], $f[[REG3]]
-; CHECK:  sdc1  $f[[REG3]], 0(${{[0-9]+}})
-; CHECK:  .end  d1
+; mip32r2:  .ent  d1
+; mips32r2:  lui  $[[REG1a:[0-9]+]], 16371
+; mips32r2:  ori  $[[REG2a:[0-9]+]], $[[REG1a]], 49353
+; mips32r2:  lui  $[[REG1b:[0-9]+]], 21403
+; mips32r2:  ori  $[[REG2b:[0-9]+]], $[[REG1b]], 34951
+; mips32r2:  mtc1  $[[REG2b]], $f[[REG3:[0-9]+]]
+; mips32r2:  mthc1  $[[REG2a]], $f[[REG3]]
+; mips32r2:  sdc1  $f[[REG3]], 0(${{[0-9]+}})
+; mips32r2:  .end  d1
+; mips32:  .ent  d1
+; mips32:  lui  $[[REG1a:[0-9]+]], 16371
+; mips32:  ori  $[[REG2a:[0-9]+]], $[[REG1a]], 49353
+; mips32:  lui  $[[REG1b:[0-9]+]], 21403
+; mips32:  ori  $[[REG2b:[0-9]+]], $[[REG1b]], 34951
+; mips32:  mtc1  $[[REG2b]], $f[[REG3:[0-9]+]]
+; mips32:  mtc1  $[[REG2a]], $f{{[0-9]+}}
+; mips32:  sdc1  $f[[REG3]], 0(${{[0-9]+}})
+; mips32:  .end  d1
+
   ret void
 }
 
 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

test/CodeGen/Mips/Fast-ISel/simplestorei.ll

 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
 ; RUN:     < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN:     < %s | FileCheck %s
 
 @ijk = external global i32
 
 ; Function Attrs: nounwind
 define void @si2_1() #0 {
 entry:
   store i32 32767, i32* @ijk, align 4
 ; CHECK:        .ent    si2_1