R600/SI: Implement getLdStBaseRegImmOfs for LDS

[arsenm]

Summary

Theoretically this should help with load / store clustering, but so far I haven't managed to get it to do anything. This will also be used to help with using read2 / write2 instructions

[arsenm]

Use getNamedOperandIdx, implement for other address spaces

[arsenm]

r214225 with getNamedOperand()

lib/Target/R600/SIInstrInfo.h

     return RI;
   }
 
+  bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
+                            unsigned &BaseReg, unsigned &Offset,
+                            const TargetRegisterInfo *TRI) const final;
+
   void copyPhysReg(MachineBasicBlock &MBB,
                    MachineBasicBlock::iterator MI, DebugLoc DL,
                    unsigned DestReg, unsigned SrcReg,

lib/Target/R600/SIInstrInfo.cpp

 // TargetInstrInfo callbacks
 //===----------------------------------------------------------------------===//
 
+bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
+                                       unsigned &BaseReg, unsigned &Offset,
+                                       const TargetRegisterInfo *TRI) const {
+  unsigned Opc = LdSt->getOpcode();
+  if (isDS(Opc)) {
+    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
+    if (OffsetIdx == -1) {
+      // The 2 offset instructions use offset0 and offset1 instead. This
+      // function only handles simple instructions with only a single offset, so
+      // we ignore them.
+      return false;
+    }
+
+    int AddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::addr);
+
+    BaseReg = LdSt->getOperand(AddrIdx).getReg();
+    Offset = LdSt->getOperand(OffsetIdx).getImm();
+    return true;
+  }
+
+  if (isMUBUF(Opc) || isMTBUF(Opc)) {
+    if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
+      return false;
+
+    int VaddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr);
+    if (VaddrIdx == -1)
+      return false;
+
+    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
+
+    BaseReg = LdSt->getOperand(VaddrIdx).getReg();
+    Offset = LdSt->getOperand(OffsetIdx).getImm();
+    return true;
+  }
+
+  if (isSMRD(Opc)) {
+    int OffsetIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::offset);
+    if (OffsetIdx == -1)
+      return false;
+
+    int SBaseIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sbase);
+
+    BaseReg = LdSt->getOperand(SBaseIdx).getReg();
+    Offset = LdSt->getOperand(OffsetIdx).getImm();
+    return true;
+  }
+
+  return false;
+}
+
 void
 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                          MachineBasicBlock::iterator MI, DebugLoc DL,