As described by the comments below, some Pats intends to generate complicated instruction sequences for the type conversion from i8 to f32 and from i16 to f64 due to performance concerns.
If an integer is about to be converted to a floating point value,
just load it on the floating point unit.
These patterns are more complex because floating point loads do not
support sign extension.
The sign extension has to be explicitly added and is only supported for
one step: byte-to-half, half-to-word, word-to-doubleword.
SCVTF GPR -> FPR is 9 cycles.
SCVTF FPR -> FPR is 4 cyclces.
(sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
and still being faster.
However, this is not good for code size.
// 8-bits -> float. 2 sizes step-up.
Unfortunately this may not be true for micro-architectures other than Cyclone.
This patch adds a new predicate for Cyclone in .td file, and disable two Pats of generating this complicated patterns, and finally we can directly generate scvtf instruction for micro-architectures other than Cyclone.