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[mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1.
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Authored by dsanders on Jul 13 2014, 5:29 AM.

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Summary

This is because the FP64A the hardware will redirect 32-bit reads/writes
from/to odd-numbered registers to the upper 32-bits of the corresponding
even register. In effect, simulating FR=0 mode when FR=0 mode is not
available.

Unfortunately, we have to make the decision to avoid mfc1/mtc1 before
register allocation so we currently do this for even registers too.

FPXX has a similar requirement on 32-bit architectures that lack
mfhc1/mthc1 so this patch also handles the affected moves from the FPU for
FPXX too. Moves to the FPU were supported by an earlier commit.

Depends on D4465, D4483

Diff Detail

Event Timeline

dsanders updated this revision to Diff 11347.Jul 13 2014, 5:29 AM
dsanders retitled this revision from to [mips] For the FP64A ABI, odd-numbered double-precision moves must not use mtc1/mfc1..
dsanders updated this object.
dsanders edited the test plan for this revision. (Show Details)
dsanders added a reviewer: sstankovic.
dsanders updated this revision to Diff 11357.Jul 13 2014, 1:13 PM

Use correct register class when obtaining the FI to use. This fixes a number of
test-suite failures.

dsanders updated this revision to Diff 11373.Jul 14 2014, 6:02 AM
dsanders edited edge metadata.

Rebase before commit.

dsanders accepted this revision.Jul 14 2014, 6:16 AM
dsanders added a reviewer: dsanders.
This revision is now accepted and ready to land.Jul 14 2014, 6:16 AM
dsanders closed this revision.Jul 14 2014, 6:16 AM