[ARM64-BE] Fix byte order of CIE and FDE frames for exception handling

[cpirker]

Summary

Hi all,

The .eh_frame section is a sequence of records.
Each record is either a CIE (Common Information Entry) or an FDE (Frame Description Entry).
Each of these records contain length and offset fields, that need to be stored in proper byte order.
ARM big endian mode requires the .eh_frame section in bit endian order, although instructions are always in le order.

This patch stores fixups in .eh_frame section in bit endian order (for be mode).

Please review.

Thanks,
Christian

[jmolloy]

Hi Christian,

This looks reasonable - I only have one comment. Can I assume there'll be an AArch32 patch coming to fix the same thing too?

Cheers,

James

lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp

540

This can be greatly simplified by using ByteSwap_32 from Support/MathExtras.h.

[cpirker]

Hi James,

For the AArch32 you can find a similar path in D3704.

Thanks,
Christian

[jmolloy]

lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp

536

Another nit: please put the * next to the variable.

[cpirker]

Hi James,

I updated as you requested.
Can you please review.

Thanks,
Christian

[cpirker]

Hi James,

Please ignore "Diff 2", I used the wrong diff file.
Can you please review "Diff 3".

Thanks,
Christian

[jmolloy]

LGTM!

[cpirker]

I committed this patch as rL208792.

lib/Target/ARM64/MCTargetDesc/ARM64AsmBackend.cpp

 #include "ARM64RegisterInfo.h"
 #include "MCTargetDesc/ARM64FixupKinds.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCDirectives.h"
 #include "llvm/MC/MCFixupKindInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MachO.h"
 using namespace llvm;
 
 namespace {
 
 class ARM64AsmBackend : public MCAsmBackend {
   static const unsigned PCRelFlagVal =
public:
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
     return createARM64ELFObjectWriter(OS, OSABI, IsLittleEndian);
   }
 
   void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
                          const MCFixup &Fixup, const MCFragment *DF,
                          const MCValue &Target, uint64_t &Value,
                          bool &IsResolved) override;
+
+  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
+                  uint64_t Value, bool IsPCRel) const override;
 };
 
 void ELFARM64AsmBackend::processFixupValue(const MCAssembler &Asm,
                                            const MCAsmLayout &Layout,
                                            const MCFixup &Fixup,
                                            const MCFragment *DF,
                                            const MCValue &Target,
                                            uint64_t &Value, bool &IsResolved) {
   // The ADRP instruction adds some multiple of 0x1000 to the current PC &
   // ~0xfff. This means that the required offset to reach a symbol can vary by
   // up to one step depending on where the ADRP is in memory. For example:
   //
   //     ADRP x0, there
   //  there:
   //
   // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
   // we'll need that as an offset. At any other address "there" will be in the
   // same page as the ADRP and the instruction should encode 0x0. Assuming the
   // section isn't 0x1000-aligned, we therefore need to delegate this decision
   // to the linker -- a relocation!
   if ((uint32_t)Fixup.getKind() == ARM64::fixup_arm64_pcrel_adrp_imm21)
     IsResolved = false;
 }
+
+void ELFARM64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
+                                    unsigned DataSize, uint64_t Value,
+                                    bool IsPCRel) const {
+  // store fixups in .eh_frame section in big endian order
+  if (!IsLittleEndian && Fixup.getKind() == FK_Data_4) {
+    const MCSection *Sec = Fixup.getValue()->FindAssociatedSection();
+    const MCSectionELF *SecELF = static_cast<const MCSectionELF *>(Sec);
+    if (SecELF->getSectionName() == ".eh_frame")
+      Value = ByteSwap_32(unsigned(Value));
+  }
+  ARM64AsmBackend::applyFixup (Fixup, Data, DataSize, Value, IsPCRel);
+}
 }
 
 MCAsmBackend *llvm::createARM64leAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
                                             StringRef TT, StringRef CPU) {
   Triple TheTriple(TT);
 
   if (TheTriple.isOSDarwin())

test/CodeGen/ARM64/big-endian-eh.ll

+; RUN: llc -mtriple arm64_be -filetype obj < %s | llvm-objdump -s - | FileCheck %s
+
+; ARM EHABI for big endian
+; This test case checks whether CIE length record is laid out in big endian format.
+;
+; This is the LLVM assembly generated from following C++ code:
+;
+; extern void foo(int);
+; void test(int a, int b) {
+;   try {
+;   foo(a);
+; } catch (...) {
+;   foo(b);
+; }
+;}
+
+define void @_Z4testii(i32 %a, i32 %b) #0 {
+entry:
+  invoke void @_Z3fooi(i32 %a)
+          to label %try.cont unwind label %lpad
+
+lpad:                                             ; preds = %entry
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* null
+  %1 = extractvalue { i8*, i32 } %0, 0
+  %2 = tail call i8* @__cxa_begin_catch(i8* %1) #2
+  invoke void @_Z3fooi(i32 %b)
+          to label %invoke.cont2 unwind label %lpad1
+
+invoke.cont2:                                     ; preds = %lpad
+  tail call void @__cxa_end_catch()
+  br label %try.cont
+
+try.cont:                                         ; preds = %entry, %invoke.cont2
+  ret void
+
+lpad1:                                            ; preds = %lpad
+  %3 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  invoke void @__cxa_end_catch()
+          to label %eh.resume unwind label %terminate.lpad
+
+eh.resume:                                        ; preds = %lpad1
+  resume { i8*, i32 } %3
+
+terminate.lpad:                                   ; preds = %lpad1
+  %4 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          catch i8* null
+  %5 = extractvalue { i8*, i32 } %4, 0
+  tail call void @__clang_call_terminate(i8* %5) #3
+  unreachable
+}
+
+declare void @_Z3fooi(i32) #0
+
+declare i32 @__gxx_personality_v0(...)
+
+declare i8* @__cxa_begin_catch(i8*)
+
+declare void @__cxa_end_catch()
+
+; Function Attrs: noinline noreturn nounwind
+define linkonce_odr hidden void @__clang_call_terminate(i8*) #1 {
+  %2 = tail call i8* @__cxa_begin_catch(i8* %0) #2
+  tail call void @_ZSt9terminatev() #3
+  unreachable
+}
+
+declare void @_ZSt9terminatev()
+
+; CHECK-LABEL: Contents of section .eh_frame:
+; CHECK-NEXT: 0000 0000001c
+