[ARM64] Recognize conditional incremental when there is ZEXT after SETCC in DAG

[weimingz]

Summary

This patch fixes bug http://llvm.org/bugs/show_bug.cgi?id=19680

[t.p.northover]

Hi Weiming,

This looks perfectly correct, but may be a bit more intelligible if you factor out a "static bool isSetCCOrZExtSetCC()" function. We could really do with a neater way to handle that nested std::swap idiom.

Anyway, I'll leave the choice up to you, no need to ask for re-review either way.

Cheers.

Tim.

[weimingz]

Thanks for reviewing, Tim. I factored out the function and committed as r208660.

lib/Target/ARM64/ARM64ISelLowering.cpp

 }
 
 // The folding we want to perform is:
-// (add x, (setcc cc ...) )
+// (add x, [zext] (setcc cc ...) )
 //   -->
 // (csel x, (add x, 1), !cc ...)
 //

   // If neither operand is a SET_CC, give up.
   if (!isSetCC(LHS, InfoAndKind)) {
     std::swap(LHS, RHS);
-    if (!isSetCC(LHS, InfoAndKind))
-      return SDValue();
+    if (!isSetCC(LHS, InfoAndKind)) {
+      // Further check if there is a ZEXT of SET_CC.
+      if (!(LHS.getOpcode() == ISD::ZERO_EXTEND &&
+            isSetCC(LHS->getOperand(0), InfoAndKind))) {
+        std::swap(LHS, RHS);
+        if (!(LHS.getOpcode() == ISD::ZERO_EXTEND &&
+              isSetCC(LHS->getOperand(0), InfoAndKind)))
+          return SDValue();
+      }
+    }
   }
 
   // FIXME: This could be generatized to work for FP comparisons.

test/CodeGen/ARM64/csel.ll

   %. = select i1 %cmp, i64 1, i64 2
   ret i64 %.
 }
+
+define i64 @foo19(i64 %a, i64 %b, i64 %c) {
+entry:
+; CHECK-LABEL: foo19:
+; CHECK: csinc x0, x2, x2
+; CHECK-NOT: add
+  %cmp = icmp ult i64 %a, %b
+  %inc = zext i1 %cmp to i64
+  %inc.c = add i64 %inc, %c
+  ret i64 %inc.c
+}