ARM: provide a generic hint intrinsic

[abdulras]

Summary

Introduce the llvm.arm.hint(i32) intrinsic that can be used to inject hints into
the instruction stream. This is particularly useful for generating IR from a
compiler where the user may inject an intrinsic (e.g. __yield). These are then
pattern substituted into the correct instruction which already existed.

[t.p.northover]

Hi Saleem,

It mostly looks straightforward, but I'd make the patterns more generic: hints 0-5 already have defined meanings, but the whole point of the instruction is that it's more generic than that. There's no particular reason to exclude any number in the space.

Cheers.

Tim.

lib/Target/ARM/ARMInstrInfo.td

1845–1850

I'd put the pattern into the generic HINT instruction: hints 0-5 have fairly tied down meanings, but the whole point of the mechanism is that it's more generic than that.

[abdulras]

Committed with the suggested changes as SVN r207242.

include/llvm/IR/IntrinsicsARM.td

def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
     [IntrNoMem]>;
 def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
     [IntrNoMem]>;
 
 //===----------------------------------------------------------------------===//
 // HINT
 def int_arm_sevl : Intrinsic<[], []>;
 
+def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
+
 //===----------------------------------------------------------------------===//
 // Advanced SIMD (NEON)
 
 // The following classes do not correspond directly to GCC builtins.
 class Neon_1Arg_Intrinsic
   : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
 class Neon_1Arg_Narrow_Intrinsic
   : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;

lib/Target/ARM/ARMInstrInfo.td

 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
 
 def : Pat<(int_arm_sevl), (HINT 5)>;
 
+def : Pat<(int_arm_hint 0), (HINT 0)>;
+def : Pat<(int_arm_hint 1), (HINT 1)>;
+def : Pat<(int_arm_hint 2), (HINT 2)>;
+def : Pat<(int_arm_hint 3), (HINT 3)>;
+def : Pat<(int_arm_hint 4), (HINT 4)>;
+def : Pat<(int_arm_hint 5), (HINT 5)>;
+
 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
              "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rm;
   let Inst{3-0} = Rm;
   let Inst{15-12} = Rd;
   let Inst{19-16} = Rn;

lib/Target/ARM/ARMInstrThumb.td

 def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110
 def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410
 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408
 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409
 def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
   let Predicates = [IsThumb2, HasV8];
 }
+
 def : T2Pat<(int_arm_sevl), (tHINT 5)>;
 
+def : T2Pat<(int_arm_hint 0), (tHINT 0)>;
+def : T2Pat<(int_arm_hint 1), (tHINT 1)>;
+def : T2Pat<(int_arm_hint 2), (tHINT 2)>;
+def : T2Pat<(int_arm_hint 3), (tHINT 3)>;
+def : T2Pat<(int_arm_hint 4), (tHINT 4)>;
+def : T2Pat<(int_arm_hint 5), (tHINT 5)>;
+
 // The imm operand $val can be used by a debugger to store more information
 // about the breakpoint.
 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
                 []>,
            T1Encoding<0b101111> {
   let Inst{9-8} = 0b10;
   // A8.6.22
   bits<8> val;

lib/Target/ARM/ARMInstrThumb2.td

 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p)> {
   let Predicates = [IsThumb2, HasV8];
 }
 
+def : Pat<(int_arm_hint 0), (t2HINT 0)>;
+def : Pat<(int_arm_hint 1), (t2HINT 1)>;
+def : Pat<(int_arm_hint 2), (t2HINT 2)>;
+def : Pat<(int_arm_hint 3), (t2HINT 3)>;
+def : Pat<(int_arm_hint 4), (t2HINT 4)>;
+def : Pat<(int_arm_hint 5), (t2HINT 5)>;
+
 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
   bits<4> opt;
   let Inst{31-20} = 0b111100111010;
   let Inst{19-16} = 0b1111;
   let Inst{15-8} = 0b10000000;
   let Inst{7-4} = 0b1111;
   let Inst{3-0} = opt;
 }

test/CodeGen/ARM/hints.ll

+; RUN: llc -mtriple armv7-eabi -o - %s | FileCheck %s
+; RUN: llc -mtriple thumb-eabi -mcpu arm1156t2-s -o - %s | FileCheck %s
+; RUN: llc -mtriple thumbv7-eabi -o - %s | FileCheck %s
+
+declare void @llvm.arm.hint(i32) nounwind
+
+define void @hint_nop() {
+  tail call void @llvm.arm.hint(i32 0) nounwind
+  ret void
+}
+
+; CHECK-LABEL: hint_nop
+; CHECK: nop
+
+define void @hint_yield() {
+  tail call void @llvm.arm.hint(i32 1) nounwind
+  ret void
+}
+
+; CHECK-LABEL: hint_yield
+; CHECK: yield
+
+define void @hint_wfe() {
+  tail call void @llvm.arm.hint(i32 2) nounwind
+  ret void
+}
+
+; CHECK-LABEL: hint_wfe
+; CHECK: wfe
+
+define void @hint_wfi() {
+  tail call void @llvm.arm.hint(i32 3) nounwind
+  ret void
+}
+
+; CHECK-LABEL: hint_wfi
+; CHECK: wfi
+
+define void @hint_sev() {
+  tail call void @llvm.arm.hint(i32 4) nounwind
+  ret void
+}
+
+; CHECK-LABEL: hint_sev
+; CHECK: sev
+
+define void @hint_sevl() {
+  tail call void @llvm.arm.hint(i32 5) nounwind
+  ret void
+}
+
+; CHECK-LABEL: hint_sevl
+; CHECK: hint #5
+