AARCH64: Implement big endian loads of NEON types from constant pools

[Konrad]

Summary

Hi,

This patch allows correct loading of vectors from constant pools in big endian mode. It's using ldn instructions instead of ldr, and preserves the little endian element order of vector constants in pools. This patch supersedes D3305, that aims for the same goal, but
different approach.

Cheers,
Conny

lib/Target/AArch64/AArch64InstrNEON.td

 //
 //===----------------------------------------------------------------------===//
 
+def IsBE          : Predicate<"!Subtarget->isLittle()">;
+def IsLE          : Predicate<"Subtarget->isLittle()">;
+
 //===----------------------------------------------------------------------===//
 // NEON-specific DAG Nodes.
 //===----------------------------------------------------------------------===//

   defm : ls_128_pats<address, Base, Offset, v2f64>;
 }
 
-defm : uimm12_neon_pats<(A64WrapperSmall
-                          tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
-                        (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
+let Predicates = [IsLE] in {
+  defm : uimm12_neon_pats<(A64WrapperSmall
+                            tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
+                          (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
+}
 
 //===----------------------------------------------------------------------===//
 // Multiclasses

test/CodeGen/AArch64/neon-vector-pool.ll

+; RUN: llc < %s -march aarch64 -mattr neon -o - | FileCheck %s -check-prefix CHECK-LE
+; RUN: llc < %s -march aarch64_be -mattr neon -o - | FileCheck %s -check-prefix CHECK-BE
+
+define void @build_const_vector_2i64( <2 x i64>* %storeaddr ) {
+; CHECK-LE-LABEL: build_const_vector_2i64:
+; CHECK-LE: ldr q
+; CHECK-BE-LABEL: build_const_vector_2i64:
+; CHECK-BE: ld1 {v0.2d}
+  store <2 x i64> < i64 64, i64 65 >, <2 x i64>* %storeaddr
+  ret void
+}
+
+define void @build_const_vector_4i32( <4 x i32>* %storeaddr ) {
+; CHECK-LE-LABEL: build_const_vector_4i32:
+; CHECK-LE: ldr q
+; CHECK-BE-LABEL: build_const_vector_4i32:
+; CHECK-BE: ld1 {v0.4s}
+  store <4 x i32> < i32 32, i32 33, i32 34, i32 35 >, <4 x i32>* %storeaddr
+  ret void
+}
+
+define void @build_const_vector_8i16( <8 x i16>* %storeaddr ) {
+; CHECK-LE-LABEL: build_const_vector_8i16:
+; CHECK-LE: ldr q
+; CHECK-BE-LABEL: build_const_vector_8i16:
+; CHECK-BE: ld1 {v0.8h}
+  store <8 x i16> < i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23 >, <8 x i16>* %storeaddr
+  ret void
+}
+
+define void @build_const_vector_16i8( <16 x i8>* %storeaddr ) {
+; CHECK-LE-LABEL: build_const_vector_16i8:
+; CHECK-LE: ldr q
+; CHECK-BE-LABEL: build_const_vector_16i8:
+; CHECK-BE: ld1 {v0.16b}
+  store <16 x i8> < i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15,
+                    i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23 >, <16 x i8>* %storeaddr
+  ret void
+}