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Differential D3321

[AArch64] Enable generating TBZ/TBNZ
ClosedPublic

Authored by zzheng on Apr 8 2014, 10:56 AM.

Details

Reviewers
t.p.northover
zzheng
Jiangning
apazos
Summary

This is one of the optimizations we ported from ARM64 to AArch64 to address the performance gap between these two back ends. Please help review.

Diff Detail

Event Timeline

Jiangning added a comment.Apr 8 2014, 11:16 PM

This looks good to me!

Thanks,
-Jiangning

2014-04-09 1:56 GMT+08:00 Z. Zheng <zhaoshiz@codeaurora.org>:

Hi Jiangning, t.p.northover,

This is one of the optimizations we ported from ARM64 to AArch64 to
address the performance gap between these two back ends. Please help review.

http://reviews.llvm.org/D3321

Files:

lib/Target/AArch64/AArch64ISelLowering.cpp
test/CodeGen/AArch64/andCmpBrToTBZ.ll

Index: lib/Target/AArch64/AArch64ISelLowering.cpp

  • lib/Target/AArch64/AArch64ISelLowering.cpp

+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -540,6 +540,8 @@

setTargetDAGCombine(ISD::SIGN_EXTEND);
setTargetDAGCombine(ISD::VSELECT);

+
+ MaskAndBranchFoldingIsLegal = true;
}

EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT)
const {

Index: test/CodeGen/AArch64/andCmpBrToTBZ.ll

  • /dev/null

+++ test/CodeGen/AArch64/andCmpBrToTBZ.ll
@@ -0,0 +1,72 @@
+; RUN: llc -O1 -march=aarch64 -enable-andcmp-sinking=true < %s |
FileCheck %s
+; ModuleID = 'and-cbz-extr-mr.bc'
+target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
+target triple = "aarch64-none-linux-gnu"
+
+define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8*
%str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8,
i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8*
%str14) unnamed_addr #0 align 2 {
+; CHECK: foo:
+entry:
+ %tobool = icmp eq i8* %str14, null
+ br i1 %tobool, label %return, label %if.end
+
+; CHECK: %if.end
+; CHECK: tbz
+if.end: ; preds = %entry
+ %and.i.i.i = and i32 %int1, 4
+ %tobool.i.i.i = icmp eq i32 %and.i.i.i, 0
+ br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i
+
+land.rhs.i: ; preds = %if.end
+ %cmp.i.i.i = icmp eq i8* %str12, %str13
+ br i1 %cmp.i.i.i, label %if.then3, label %lor.rhs.i.i.i
+
+lor.rhs.i.i.i: ; preds = %land.rhs.i
+ %cmp.i13.i.i.i = icmp eq i8* %str10, %str11
+ br i1 %cmp.i13.i.i.i, label
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, label %if.end5
+
+_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds =
%lor.rhs.i.i.i
+ %cmp.i.i.i.i = icmp eq i8* %str8, %str9
+ br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5
+
+if.then3: ; preds =
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i
+ %tmp11 = load i8* %str14, align 8
+ %tmp12 = and i8 %tmp11, 2
+ %tmp13 = icmp ne i8 %tmp12, 0
+ br label %return
+
+if.end5: ; preds =
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %lor.rhs.i.i.i
+; CHECK: %if.end5
+; CHECK: tbz
+ br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19
+
+land.rhs.i19: ; preds = %if.end5
+ %cmp.i.i.i18 = icmp eq i8* %str6, %str7
+ br i1 %cmp.i.i.i18, label %if.then7, label %lor.rhs.i.i.i23
+
+lor.rhs.i.i.i23: ; preds = %land.rhs.i19
+ %cmp.i13.i.i.i22 = icmp eq i8* %str3, %str4
+ br i1 %cmp.i13.i.i.i22, label
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, label %if.end12
+
+_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28: ; preds =
%lor.rhs.i.i.i23
+ %cmp.i.i.i.i26 = icmp eq i8* %str1, %str2
+ br i1 %cmp.i.i.i.i26, label %if.then7, label %if.end12
+
+if.then7: ; preds =
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %land.rhs.i19
+ br i1 %isTextField, label %if.then9, label %if.end12
+
+if.then9: ; preds = %if.then7
+ %tmp23 = load i8* %str5, align 8
+ %tmp24 = and i8 %tmp23, 2
+ %tmp25 = icmp ne i8 %tmp24, 0
+ br label %return
+
+if.end12: ; preds = %if.then7,
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28,
%lor.rhs.i.i.i23, %if.end5, %if.end
+ %lnot = xor i1 %IsEditable, true
+ br label %return
+
+return: ; preds = %if.end12,
%if.then9, %if.then3, %entry
+ %retval.0 = phi i1 [ %tmp13, %if.then3 ], [ %tmp25, %if.then9 ], [
%lnot, %if.end12 ], [ true, %entry ]
+ ret i1 %retval.0
+}
+
+attributes #0 = { nounwind ssp }

zzheng updated this revision to Unknown Object (????).Apr 17 2014, 5:55 PM

Rebased, no code change.

Reviewers, I don't have commit access. Please merge it, Thanks in advance.

Jiangning added a comment.Apr 17 2014, 11:05 PM

Committed as r206559.

Thanks,
-Jiangning

2014-04-18 8:55 GMT+08:00 Z. Zheng <zhaoshiz@codeaurora.org>:

Rebased, no code change.

Reviewers, I don't have commit access. Please merge it, Thanks in

advance.

Hi Jiangning, t.p.northover, apazos,

http://reviews.llvm.org/D3321

CHANGE SINCE LAST DIFF

http://reviews.llvm.org/D3321?vs=8430&id=8619#toc

Files:

lib/Target/AArch64/AArch64ISelLowering.cpp
test/CodeGen/AArch64/andCmpBrToTBZ.ll

Index: lib/Target/AArch64/AArch64ISelLowering.cpp

  • lib/Target/AArch64/AArch64ISelLowering.cpp

+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -540,6 +540,8 @@

setTargetDAGCombine(ISD::SIGN_EXTEND);
setTargetDAGCombine(ISD::VSELECT);

+
+ MaskAndBranchFoldingIsLegal = true;
}

EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT)
const {

Index: test/CodeGen/AArch64/andCmpBrToTBZ.ll

  • /dev/null

+++ test/CodeGen/AArch64/andCmpBrToTBZ.ll
@@ -0,0 +1,72 @@
+; RUN: llc -O1 -march=aarch64 -enable-andcmp-sinking=true < %s |
FileCheck %s
+; ModuleID = 'and-cbz-extr-mr.bc'
+target datalayout =
"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
+target triple = "aarch64-none-linux-gnu"
+
+define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8*
%str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8,
i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8*
%str14) unnamed_addr #0 align 2 {
+; CHECK: foo:
+entry:
+ %tobool = icmp eq i8* %str14, null
+ br i1 %tobool, label %return, label %if.end
+
+; CHECK: %if.end
+; CHECK: tbz
+if.end: ; preds = %entry
+ %and.i.i.i = and i32 %int1, 4
+ %tobool.i.i.i = icmp eq i32 %and.i.i.i, 0
+ br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i
+
+land.rhs.i: ; preds = %if.end
+ %cmp.i.i.i = icmp eq i8* %str12, %str13
+ br i1 %cmp.i.i.i, label %if.then3, label %lor.rhs.i.i.i
+
+lor.rhs.i.i.i: ; preds = %land.rhs.i
+ %cmp.i13.i.i.i = icmp eq i8* %str10, %str11
+ br i1 %cmp.i13.i.i.i, label
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, label %if.end5
+
+_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds =
%lor.rhs.i.i.i
+ %cmp.i.i.i.i = icmp eq i8* %str8, %str9
+ br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5
+
+if.then3: ; preds =
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i
+ %tmp11 = load i8* %str14, align 8
+ %tmp12 = and i8 %tmp11, 2
+ %tmp13 = icmp ne i8 %tmp12, 0
+ br label %return
+
+if.end5: ; preds =
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %lor.rhs.i.i.i
+; CHECK: %if.end5
+; CHECK: tbz
+ br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19
+
+land.rhs.i19: ; preds = %if.end5
+ %cmp.i.i.i18 = icmp eq i8* %str6, %str7
+ br i1 %cmp.i.i.i18, label %if.then7, label %lor.rhs.i.i.i23
+
+lor.rhs.i.i.i23: ; preds = %land.rhs.i19
+ %cmp.i13.i.i.i22 = icmp eq i8* %str3, %str4
+ br i1 %cmp.i13.i.i.i22, label
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, label %if.end12
+
+_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28: ; preds =
%lor.rhs.i.i.i23
+ %cmp.i.i.i.i26 = icmp eq i8* %str1, %str2
+ br i1 %cmp.i.i.i.i26, label %if.then7, label %if.end12
+
+if.then7: ; preds =
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %land.rhs.i19
+ br i1 %isTextField, label %if.then9, label %if.end12
+
+if.then9: ; preds = %if.then7
+ %tmp23 = load i8* %str5, align 8
+ %tmp24 = and i8 %tmp23, 2
+ %tmp25 = icmp ne i8 %tmp24, 0
+ br label %return
+
+if.end12: ; preds = %if.then7,
%_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28,
%lor.rhs.i.i.i23, %if.end5, %if.end
+ %lnot = xor i1 %IsEditable, true
+ br label %return
+
+return: ; preds = %if.end12,
%if.then9, %if.then3, %entry
+ %retval.0 = phi i1 [ %tmp13, %if.then3 ], [ %tmp25, %if.then9 ], [
%lnot, %if.end12 ], [ true, %entry ]
+ ret i1 %retval.0
+}
+
+attributes #0 = { nounwind ssp }

zzheng accepted this revision.Oct 31 2014, 10:44 AM
zzheng added a reviewer: zzheng.
This revision is now accepted and ready to land.Oct 31 2014, 10:44 AM
zzheng closed this revision.Oct 31 2014, 10:45 AM

Revision Contents

PathSize
lib/
Target/
AArch64/
2 lines
test/
CodeGen/
AArch64/
72 lines

Diff 8619

lib/Target/AArch64/AArch64ISelLowering.cpp

Context not available.
setTargetDAGCombine(ISD::SIGN_EXTEND); setTargetDAGCombine(ISD::SIGN_EXTEND);
setTargetDAGCombine(ISD::VSELECT); setTargetDAGCombine(ISD::VSELECT);
MaskAndBranchFoldingIsLegal = true;
} }
EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
Context not available.

test/CodeGen/AArch64/andCmpBrToTBZ.ll

  • This file was added.
; RUN: llc -O1 -march=aarch64 -enable-andcmp-sinking=true < %s | FileCheck %s
; ModuleID = 'and-cbz-extr-mr.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128"
target triple = "aarch64-none-linux-gnu"
define zeroext i1 @foo(i1 %IsEditable, i1 %isTextField, i8* %str1, i8* %str2, i8* %str3, i8* %str4, i8* %str5, i8* %str6, i8* %str7, i8* %str8, i8* %str9, i8* %str10, i8* %str11, i8* %str12, i8* %str13, i32 %int1, i8* %str14) unnamed_addr #0 align 2 {
; CHECK: foo:
entry:
%tobool = icmp eq i8* %str14, null
br i1 %tobool, label %return, label %if.end
; CHECK: %if.end
; CHECK: tbz
if.end: ; preds = %entry
%and.i.i.i = and i32 %int1, 4
%tobool.i.i.i = icmp eq i32 %and.i.i.i, 0
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i
land.rhs.i: ; preds = %if.end
%cmp.i.i.i = icmp eq i8* %str12, %str13
br i1 %cmp.i.i.i, label %if.then3, label %lor.rhs.i.i.i
lor.rhs.i.i.i: ; preds = %land.rhs.i
%cmp.i13.i.i.i = icmp eq i8* %str10, %str11
br i1 %cmp.i13.i.i.i, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, label %if.end5
_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds = %lor.rhs.i.i.i
%cmp.i.i.i.i = icmp eq i8* %str8, %str9
br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5
if.then3: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i
%tmp11 = load i8* %str14, align 8
%tmp12 = and i8 %tmp11, 2
%tmp13 = icmp ne i8 %tmp12, 0
br label %return
if.end5: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %lor.rhs.i.i.i
; CHECK: %if.end5
; CHECK: tbz
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19
land.rhs.i19: ; preds = %if.end5
%cmp.i.i.i18 = icmp eq i8* %str6, %str7
br i1 %cmp.i.i.i18, label %if.then7, label %lor.rhs.i.i.i23
lor.rhs.i.i.i23: ; preds = %land.rhs.i19
%cmp.i13.i.i.i22 = icmp eq i8* %str3, %str4
br i1 %cmp.i13.i.i.i22, label %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, label %if.end12
_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28: ; preds = %lor.rhs.i.i.i23
%cmp.i.i.i.i26 = icmp eq i8* %str1, %str2
br i1 %cmp.i.i.i.i26, label %if.then7, label %if.end12
if.then7: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %land.rhs.i19
br i1 %isTextField, label %if.then9, label %if.end12
if.then9: ; preds = %if.then7
%tmp23 = load i8* %str5, align 8
%tmp24 = and i8 %tmp23, 2
%tmp25 = icmp ne i8 %tmp24, 0
br label %return
if.end12: ; preds = %if.then7, %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit28, %lor.rhs.i.i.i23, %if.end5, %if.end
%lnot = xor i1 %IsEditable, true
br label %return
return: ; preds = %if.end12, %if.then9, %if.then3, %entry
%retval.0 = phi i1 [ %tmp13, %if.then3 ], [ %tmp25, %if.then9 ], [ %lnot, %if.end12 ], [ true, %entry ]
ret i1 %retval.0
}
attributes #0 = { nounwind ssp }